A 100Gb/s PAM-4 Receiver Analog Front-End

Liu，Yang1,2; Xu，Xiuli1,3; Pan，Quan4; Liu，Jian1,2; Liu，Liyuan1,2; Qi，Nan1,2; Wu，Nanjian1,2

10.1109/ICTA48799.2019.9012879

2019-11-01

978-1-7281-5041-3

2019 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019 - Proceedings

87-88

13-15 Nov. 2019

Chengdu, China

This paper describes an inverter-based receiver analog front-end design using T-coil technique implemented in a 40nm CMOS process. The proposed T-coil can separate the capacitance of PAD and preamplifier itself, to achieve a total bandwidth enhancement ratio of 2.7. The proposed continuous time linear equalizer(CTLE) adopts a negative feedback loop to generate low frequency zero-pole pair to slower down the compensation slope. The simulation result shows that the transimpedance gain of the system is 76.5 dBΩ under the bandwidth of 37GHz. The input referred noise current in maximum gain mode is 2.3uArms.

CTLE receiver analog front-end T-Coil TIA

其他

英语

EI

20201208328471

Bandwidth ; Continuous time systems ; Feedback

Information Theory and Signal Processing:716.1 ; Control Systems:731.1 ; Systems Science:961

2-s2.0-85081968302

Scopus

1.Institute of Semiconductors,Chinese Academy of Science,Beijing,China
2.University of Chinese Academy of Sciences,Beijing,China
3.University of Sciences and Technology of China,Hefei,China
4.Southern University of Science and Technology,Department of Electrical and Electronic Engineering,China

Liu，Yang,Xu，Xiuli,Pan，Quan,et al. A 100Gb/s PAM-4 Receiver Analog Front-End[C],2019:87-88.