An 18-Gb/s 36× 13 -μ M2 3.53-mW\ 27-1 PRBS Generator in 40-nm CMOS

Hu，Junfeng1; Zhani，Zhao2; Huang，Qiwei1; Yang，Jian1; Hu，Meihuang1; Jiang，Qiyao1; Guo，Yuhao1; Pan，Quan1

10.1109/ICEIC49074.2020.9051329

2020

978-1-7281-6290-4

2020 International Conference on Electronics, Information, and Communication, ICEIC 2020

1-2

19-22 Jan. 2020

Barcelona, Spain

This paper presents an 18 Gb/s\ 27-1 pseudo-random binary sequence (PRBS) generator. In the proposed PRBS, two extended truly-single-phase clock (E-TPSC) logic based DFFs are used to shorten the critical path delay and thus improve the data rate. The rest five DFFs are implemented in TSPC logic to save power consumption. Both E-TSPC and TSPC DFF occupy small area. This PRBS is designed in 40-nm CMOS. The post-layout simulation results show 18-Gb/s data rate, 36× 13-μ m core area, 3.S3-mW dc power, and 0.028-pJ/bit FOM.

E-TSPC Low power Pseudo-random binary sequence generator (PRBS) Small area TSPC

第一

英语

EI

20201708510802

Computer circuits ; Binary sequences

Semiconductor Devices and Integrated Circuits:714.2 ; Computer Theory, Includes Formal Logic, Automata Theory, Switching Theory, Programming Theory:721.1 ; Computer Circuits:721.3

2-s2.0-85083484708

Scopus

1.School of Microelectronics,Southern University of Science and Technology,Shenzhen,China
2.Graduate School of Advanced Sciences of Matter,Hiroshima University,Higashi-Hiroshima,Japan

Hu，Junfeng,Zhani，Zhao,Huang，Qiwei,et al. An 18-Gb/s 36× 13 -μ M2 3.53-mW\ 27-1 PRBS Generator in 40-nm CMOS[C],2020:1-2.