A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS

Li，Zhenghao1; Tang，Minzhe1; Fan，Taiyang1; Pan，Quan2

2021-09

10.1109/TCSII.2021.3074384

IEEE Transactions on Circuits and Systems II: Express Briefs   影响因子和分区

1558-3791

Analog front-end CTLE PAM4 receiver source follower TIA VGA

SCI ; CPCI-S ; EI

第一

20211710259501

Bandwidth ; Buffer amplifiers ; CMOS integrated circuits ; Continuous time systems ; Differential amplifiers ; Electric inverters ; Pulse amplitude modulation ; Resistors ; Voltage regulators

Amplifiers:713.1 ; Semiconductor Devices and Integrated Circuits:714.2 ; Information Theory and Signal Processing:716.1 ; Control Equipment:732.1 ; Systems Science:961

IEEE

1.School of Microelectronics, and Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen 518055, China.
2.School of Microelectronics, and Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen 518055, China. (e-mail: panq@sustech.edu.cn)

Li，Zhenghao,Tang，Minzhe,Fan，Taiyang,et al. A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs,2021,68(9):3058-3062.

Li，Zhenghao,Tang，Minzhe,Fan，Taiyang,&Pan，Quan.(2021).A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS.IEEE Transactions on Circuits and Systems II: Express Briefs,68(9),3058-3062.

Li，Zhenghao,et al."A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS".IEEE Transactions on Circuits and Systems II: Express Briefs 68.9(2021):3058-3062.