A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing

There is an emerging need to optimize floating-point (FP) dotproductunits (DPU)for high-performance scientific computing as well as training deep learning models. Due to different precision requirements of applications, a reconfigurable multiple-precision DPUoperation can largely reduce the cost of area and power. However, the existing methods could result in redundant bits for unit multipliers, but also leave idle hardware resources for the operations in different precisions. In this paper, a reconfigurable multiple-precision FP DPUdesign is proposed for high-performance computing (HPC) applications. The FP DPUcan be reconfigured as follows. A bit-partitioning method is provided to minimize the redundant bits with a configurable mixed-precision multiplier forthree-mode operations: 20 half-precision Dot Product (DP), 5 single-precision DP, and 1 double-precision DPoperations. Any of the modescan be executed in two successive clock cycles without idle hardware resources. The proposed design is realized by using theUMC 55-nm process with simulation results. Compared with the existing multiple-precision FP methods, the proposed DPUachieves88.9% and 35.8% area-saving performance for FP16 and FP32 operations,respectively. Moreover, when using benchmarked HPC applications where multiple precisions can be used,the proposed reconfigurable DPUcan accelerate up to 4× and 20× maximumthroughput rates when compared with fixed FP32 and FP64 operations, respectively.