A DESIGN OF OUTPUT-CAPACITORLESS LOW-DROPOUT REGULATOR WITH FAST TRANSIENT RESPONSE

一种具有快速瞬态响应的无片外电容型LDO设计

陈雨田

11930203

硕士

材料工程

李携曦

2021-05-18

2021-06-18

南方科技大学

深圳

With the continuous development of mobile smart devices, the demand for power management chips with high performance is increasing. As a kind of power management chip, the low-dropout regulator (LDO) has the advantages of small chip area, low power consumption, good power supply suppression characteristics, and high-power density. Compared with traditional LDOs, output-capacitorless LDOs (OCL-LDO) are more convenient for SoC integration due to the structural features that do not need the external bulky capacitors. This thesis introduces the latest research trends and the development prospects of the LDO regulator firstly. Then the basic working principle of the LDO regulator is analyzed and the thesis mainly focuses on the transient response of the LDO with the low quiescent current. Finally, this thesis gives the simulation results of the overall circuit, which verifies the function and performance of the designed circuit. The transient enhancement modules are added for the designed OCL-LDO in this thesis. The transient enhancement modules will not work when the LDO works normally while the modules are activated and generate additional current to pull up/down the gate of the power transistor when the load jumps, which improves the slew rate of the gate of the power transistor. The overshoot/undershoot voltage will be suppressed and a good load transient response performance is achieved.The TSMC 0.18 μm process is adopted in this design and the simulation environment is the Spectre. The occupied area is about 0.009 mm^2. The simulation results show that the phase margin of the designed LDO is maintained between 60° and 90° within the load current range of 1 fA to 20 mA which reveals good stability. The maximum undershoot voltage of the LDO is 55 mV when the load current steps from 1 mA to 20 mA with 400 ns. Meanwhile, the maximum overshoot voltage is 17 mV when the load current steps from 20 mA to 1 mA under the same condition, indicating that the designed circuit has good transient response capabilities as expected. Moreover, the quiescent current is only 700 nA which is especially suitable for the IoTs and the designed LDO has wide application prospect in the background of low power tendency.

随着移动智能设备的不断发展，对高性能电源管理芯片的需求不断增长。低压差线性稳压器(LDO)作为电源管理芯片的一种，具有面积小，功耗低，电源纹波抑制特性强和功率密度高等优点。与传统的LDO相比，无输出电容型LDO (OCL-LDO)由于不需要片外电容的结构特性，更便于SoC集成。本文首先介绍了LDO的最新研究趋势和未来的发展前景。然后分析了LDO的基本工作原理，其中本次设计的LDO主要研究了低静态电流下LDO的瞬态响应特性。最后，本文仿真了整个电路的各项特性，验证了本次设计电路的性能。本文设计的无片外电容型低压差线性稳压器增加了瞬态响应辅助模块。当负载没有发生跳变时，LDO正常工作，瞬态响应辅助模块被关断。当负载发生跳变的一瞬间，瞬态响应辅助模块被唤醒，并且在负载跳变时会产生额外的电流来上拉/下拉功率晶体管的栅极，从而提高了功率晶体管栅极的电压转换速率。因此过冲电压将得到很好的抑制，并实现了良好的负载瞬态响应性能。本设计采用TSMC 0.18μm工艺，所用仿真软件是Cadence公司的Spectre, 芯片有效面积约为0.009平方毫米。仿真结果表明，在1fA至20mA的负载电流范围内，所设计LDO的相位裕度保持在60°至90°之间，这展现了良好的稳定性。当负载电流从1mA跳变到20mA（在400ns内）时，LDO的最大下冲电压为55mV。同时，在相同条件下负载电流从20mA跳变至1mA时，最大过冲电压为17 mV，这表明所设计的电路具有预期的良好瞬态响应能力。 而且，静态电流仅为700 nA，这特别适合于物联网等应用，在当前趋向于低功耗的背景下具有广阔的应用前景。

LDO fully-on-chip low quiescent current fast transient response

低压差线性稳压器 无片外电型 LDO 低静态电流 快速瞬态响应

英语

独立培养

南方科技大学

Chen YT. A DESIGN OF OUTPUT-CAPACITORLESS LOW-DROPOUT REGULATOR WITH FAST TRANSIENT RESPONSE[D]. 深圳. 南方科技大学,2021.