An area-efficient low quiescent current output capacitor-less LDO with fast transient response

A Power-area-efficient output-capacitorless low-dropout (OCL-LDO) regulator with fast transient response is presented in this paper. The proposed technique permits the regulator to achieve small undershoot (overshoot) when the load steps up (down) and consumes little extra power. The proposed LDO regulator has been implemented and fabricated in a 0.18-μm CMOS process. It occupies an active area of 0.0071mm. The simulated results have shown that the proposed circuit consumes a quiescent current of 0.7 μA at no load, regulating the output at 0.7 V from a voltage supply of 0.9 V. The simulated transient output voltage is 47 mV when load current is stepped from 1 mA to 20 mA in 400 ns with CL =10 pF. Meanwhile, this circuit shows a good of figure-of-merit (FOM).