An FPGA-based high-throughput packet classification architecture supporting dynamic updates for large-scale rule sets

Xin，Yao1; Li，Wenjun1,2; Wang，Yi1,3; Yao，Song4

10.1109/INFOCOMWKSHPS51825.2021.9484440

2021-05-10

978-1-6654-4714-0

IEEE INFOCOM 2021 - IEEE Conference on Computer Communications Workshops, INFOCOM WKSHPS 2021

1-2

10-13 May 2021

Vancouver, BC, Canada

A high-performance packet classification architecture based on FPGA supporting large-scale rule sets up to 100k is proposed in this poster. It supports fast dynamic rule update and tree reconstruction. The update throughput is comparable to that of classification. An efficient data structure set for decision tree is constructed to convert tree traversal to addressing process. Different levels of parallelism are fully explored with multi-core, multi-search-engine and coarse-grained pipeline. It achieves a peak throughput of more than 1000 MPPS for 10k and 1k rule set for both classification and update.

Conferences Pipelines Parallel processing Throughput Data structures Decision trees Field programmable gate arrays

其他

英语

EI

20213410816709

Decision trees ; Field programmable gate arrays (FPGA) ; Search engines ; Trees (mathematics)

Logic Elements:721.2 ; Computer Systems and Equipment:722 ; Computer Software, Data Handling and Applications:723 ; Combinatorial Mathematics, Includes Graph Theory, Set Theory:921.4

2-s2.0-85113343697

Scopus

1.Peng Cheng Laboratory,
2.Peking University,
3.Southern University of Science and Technology,
4.New H3C,China

Xin，Yao,Li，Wenjun,Wang，Yi,et al. An FPGA-based high-throughput packet classification architecture supporting dynamic updates for large-scale rule sets[C],2021:1-2.