Identifying the Location of Hole-Induced Gate Degradation in LPCVD-SiNx/GaN MIS-FETs under High Reverse-Bias Stress

Zheng, Zheyang1; Hua, Mengyuan2; Wei, Jin1; Zhang, Zhaofu1; Chen, Kevin J.1

2019

1063-6854

2019 31ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD)

435-438

345 E 47TH ST, NEW YORK, NY 10017 USA

IEEE

When SiNx/GaN MIS-FETs are under high reverse-bias stress, holes can be generated by impact ionization, leak to gate electrode through the gate dielectric and generate defects that induce V-TH instability. In this work, we identify the location of such degradation by separately probing V-TH at source-side and drain-side of the MIS channel. It is revealed that the hole-induced gate degradation under the reverse-bias stress is more uniformly distributed along the gate with a less negative V-GS. As a result, the stability of device under high reverse-bias stress is enhanced. To further suppress the degradation, holes should be prevented from either going through or accumulating under the gate dielectric.

LPCVD SiNx/GaN MIS-FET Hole-induced degradation Hole-barrier-free Location identification E-field uniformity

其他

英语

CPCI-S

Hong Kong Innovation Technology Fund[ITS/412/17FP]

Computer Science ; Engineering

Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic

WOS:000484987200107

Web of Science

1.Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Hong Kong, Peoples R China
2.Southern Univ Sci & Technol, Dept Elect & Elect Engn, Shenzhen, Peoples R China

Zheng, Zheyang,Hua, Mengyuan,Wei, Jin,et al. Identifying the Location of Hole-Induced Gate Degradation in LPCVD-SiNx/GaN MIS-FETs under High Reverse-Bias Stress[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2019:435-438.