南方科技大学知识苑(SUSTech KC): A Chip-Area-Efficient Subthreshold CMOS Voltage Reference with High PSRR Based on Compensated. VGS of NMOS Transistors

题名	A Chip-Area-Efficient Subthreshold CMOS Voltage Reference with High PSRR Based on Compensated. VGS of NMOS Transistors
作者	Lei, Yu; Zhan, Chenchang; Huang, Chenyu; Wang, Lidan
通讯作者	Lei, Yu
发表日期	2018
会议录名称	2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018)
页码	497-500
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
摘要	A chip-area-efficient subthreshold CMOS voltage reference (CVR) with low power consumption and high power supply ripple rejection (PSRR) based on compensated. VGS of NMOS transistors is proposed in this paper. The. VGS of two different-Vth NMOS transistors is designed to achieve zero temperature coefficient (TC) by compensating its complementary -to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) components. An error amplifier driving a current mirror is then used to duplicate the generated zero-TC. VGS to a diode-connected NMOS and provide the low-TC V-REF. Only two branches are needed in the core part and no resistors are used. Consequently, low power and small area consumptions are achieved with high PSRR. A prototype design is fabricated in a standard 0.18-mu m CMOS process. An average TC of 27.26 ppm/degrees C is measured across 6 dies with a standard derivation of 16.40 ppm/degrees C over -40 to 80 degrees C temperature range. The measured line sensitivity is 0.12%/V. The measured PSRR is better than -62.7dB from 10 kHz to 10 MHz. The power consumption is as small as 17.3nW and the chip area is only 0.0244mm(2).
关键词	Subthreshold CMOS voltage reference low power consumption high power supply ripple rejection
学校署名	第一 ; 通讯
语种	英语
相关链接	[来源记录]
收录类别	CPCI-S
资助项目	Shenzhen Science and Technology Innovation Committee (STSTI)[JCYJ20160530191008447]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000458319800121
来源库	Web of Science
引用统计	被引频次[WOS]：2
成果类型	会议论文
条目标识符	http://sustech.caswiz.com/handle/2SGJ60CL/24608
专题	南方科技大学工学院_深港微电子学院
作者单位	Southern Univ Sci & Technol SUSTech, Dept EEE, Shenzhen, Peoples R China
第一作者单位	南方科技大学
通讯作者单位	南方科技大学
第一作者的第一单位	南方科技大学
推荐引用方式 GB/T 7714	Lei, Yu,Zhan, Chenchang,Huang, Chenyu,et al. A Chip-Area-Efficient Subthreshold CMOS Voltage Reference with High PSRR Based on Compensated. VGS of NMOS Transistors[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2018:497-500.