题名 | A Low-Complexity Fast-Locking Digital PLL With Multi-Output Bang-Bang Phase Detector |
作者 | |
通讯作者 | Zhan, Chenchang |
DOI | |
发表日期 | 2016
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ISBN | 978-1-5090-1571-9
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会议录名称 | |
页码 | 418-420
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会议日期 | 25-28 Oct. 2016
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会议地点 | Jeju, Korea, Republic of
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出版地 | 345 E 47TH ST, NEW YORK, NY 10017 USA
|
出版者 | |
摘要 | This paper presents a locking-accelerated DPLL based on multi-output bang-bang phase detector (MOBBPD) with reused most significant hits (MSBs). The hang-hang structure has simple implementation by eliminating the sensitive time-to-digital converter (TDC), while MOBBPD allows for reduced loop locking-time due to the multi-output. To further accelerate the loop locking, a scheme of reusing the MSBs is proposed to signify the large phase-difference at the early stage of lock acquisition, hence reducing the phase difference quickly. The low complexity of the design is maintained due to the simple structure. The proposed DPLL is designed using a 0.18-mu m CMOS process. It generates an output clock frequency range of 1-2.2 GHz with 7.8-17.2 MHz input reference frequency. The power consumption is 5.1 mW while the locking speed is improved by around 20 times improvement compared to without reusing the MSBs. |
关键词 | |
学校署名 | 第一
; 通讯
|
语种 | 英语
|
相关链接 | [来源记录] |
收录类别 | |
WOS研究方向 | Engineering
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WOS类目 | Engineering, Electrical & Electronic
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WOS记录号 | WOS:000392651200109
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EI入藏号 | 20170603321714
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EI主题词 | Frequency converters
; Locks (fasteners)
; Phase locked loops
; Signal detection
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EI分类号 | Electronic Circuits Other Than Amplifiers, Oscillators, Modulators, Limiters, Discriminators or Mixers:713.5
; Information Theory and Signal Processing:716.1
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来源库 | Web of Science
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全文链接 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7803991 |
引用统计 |
被引频次[WOS]:6
|
成果类型 | 会议论文 |
条目标识符 | http://sustech.caswiz.com/handle/2SGJ60CL/24901 |
专题 | 工学院_电子与电气工程系 |
作者单位 | 1.Southern Univ Sci & Technol, Dept Elect & Elect Engn, Shenzhen, Peoples R China 2.Sogang Univ, Dept Elect Engn, Seoul, South Korea |
第一作者单位 | 电子与电气工程系 |
通讯作者单位 | 电子与电气工程系 |
第一作者的第一单位 | 电子与电气工程系 |
推荐引用方式 GB/T 7714 |
Huang, Qiwei,Zhan, Chenchang,Burm, Jinwook,et al. A Low-Complexity Fast-Locking Digital PLL With Multi-Output Bang-Bang Phase Detector[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2016:418-420.
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条目包含的文件 | 条目无相关文件。 |
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