An Ultra-Low Power and Offset-Insensitive CMOS Subthreshold Voltage Reference

Wang, Lidan1,2; Zhan, Chenahang1; Li, Guofeng2

10.1109/APCCAS.2016.7803944

2016

978-1-5090-1571-9

2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)

243-246

25-28 Oct. 2016

Jeju, Korea, Republic of

345 E 47TH ST, NEW YORK, NY 10017 USA

IEEE

An ultra-low power and offset-insensitive CMOS voltage reference circuit is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed circuit can suppress the DC offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions, and improving the power supply ripple rejection (PSRR) are presented. The voltage reference is implemented in a 0.18-mu m CMOS process. Simulation results show that the reference can run with 0.8 V supply voltage, while the power consumption is only 62nW, and the PSRR of better than -43 dB over the full frequency range is achieved.

CMOS voltage reference subthreshold law voltage low power: power supply ripple rejection

第一 ; 通讯

英语

CPCI-S ; EI

SZSTI[JCYJ20160429191518358]

Engineering

Engineering, Electrical & Electronic

WOS:000392651200064

20170603321770

CMOS integrated circuits ; Voltage measurement

Semiconductor Devices and Integrated Circuits:714.2 ; Electric Variables Measurements:942.2

Web of Science

1.Southern Univ Sci & Technol, Dept Elect & Elect Engn, Shenzhen, Peoples R China
2.Nankai Univ, Coll Elect Informat & Opt Engn, Tianjin, Peoples R China

Wang, Lidan,Zhan, Chenahang,Li, Guofeng. An Ultra-Low Power and Offset-Insensitive CMOS Subthreshold Voltage Reference[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2016:243-246.