Research on Power Device Structure Based on FO Package Method

Song，Guan Qiang1; Huo，Jia Ren1; Wang，Juntao1; Liu，Debo1; Zhang，Chenwei2; Jiang，Jing1; Ye，Huaiyu3

10.1109/ICEPT52650.2021.9568216

2021-09-14

978-1-6654-1392-3

2021 22nd International Conference on Electronic Packaging Technology, ICEPT 2021

1-6

14-17 Sept. 2021

Xiamen, China

Most of the existing power chips are connected by wire bonding or copper sheet welding. With the development of high performance, small size, modularity and high power density of power devices, the packaging method starts to develop towards FO(Fan-out)-based packaging technology. This scheme can be designed with complex line layout and flexible metal shape linkage method. And it is a high efficiency package method with low parasitic capacitance, inductance, very low mathrmR_dson and excellent heat dissipation at high frequency. The thermal stress problem in reflow soldering is a key research object in device development, and this paper mainly focuses on the research of DFN3030 product structure based on FO package thermal stress. Using finite element software to establish a three-dimensional model, the main factors affecting the metal shape of the chip surface, copper thickness, and plastic sealing material thickness are simulated and analyzed. The simulation is used to determine the relationship between different factors affecting thermal stress, and two different structural solutions are selected for sample verification to confirm whether the simulation structure matches the actual product result trend. Through the actual product reliability verification, it is confirmed that the thermal stress trend of the actual product matches with the theoretical results. And through the sample verification, the product with FO package DFN3030 meets the reliability requirements of MSL3, TC 500cyclesat the(-55125 °C), PCT 96Hat the(120 °C, 100%RH), HTSL 1000H@150°C, THB 1000Hat the(85 °C, 85%RH).

FO packages power devices thermal simulation thermal stress

其他

英语

EI

20214511119560

Capacitance ; Copper ; Three dimensional integrated circuits

Copper:544.1 ; Electricity: Basic Concepts and Phenomena:701.1 ; Semiconductor Devices and Integrated Circuits:714.2 ; Physical Properties of Gases, Liquids and Solids:931.2

2-s2.0-85118441193

Scopus

1.Product Research and Development,Sky Chip Interconnection Technology CO. Ltd,Shenzhen,China
2.Southern University of Science and Technology,Shenzhen,China
3.Southern University of Science and Technology,Shenzhen Institute of Wide-Bandgap Semiconductors,School of Microelectronics,Shenzhen,China

Song，Guan Qiang,Huo，Jia Ren,Wang，Juntao,et al. Research on Power Device Structure Based on FO Package Method[C],2021:1-6.