A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme

Xiao，Wenbo1; Huang，Qiwei1; Mosalam，Hamed2; Zhan，Chenchang1; Li，Zhiqun3; Pan，Quan4

2022-02

10.1109/TCSI.2021.3119907

IEEE Transactions on Circuits and Systems I: Regular Papers   影响因子和分区

1558-0806

Frequency capturing half rate injection-type CDR ILDCO phase reset reference-free

SCI ; EI

第一

20214511130437

Circuit oscillations ; Clock and data recovery circuits (CDR circuits) ; Clocks ; CMOS integrated circuits ; Edge detection ; Phase comparators ; Variable frequency oscillators

Electric Networks:703.1 ; Oscillators:713.2 ; Electronic Circuits Other Than Amplifiers, Oscillators, Modulators, Limiters, Discriminators or Mixers:713.5 ; Semiconductor Devices and Integrated Circuits:714.2 ; Special Purpose Instruments:943.3

IEEE

1.School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen 518055, China.
2.School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science andTechnology, Shenzhen 518055, China, and also with the Microelectronics Department, Electronics Research Institute, Cairo 71515, Egypt.
3.Institute of RF-&OE-ICs, Southeast University, Nanjing 210096, China.
4.School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen 518055, China (e-mail: panq@sustech.edu.cn)

Xiao，Wenbo,Huang，Qiwei,Mosalam，Hamed,等. A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2022,69(2):634-644.

Xiao，Wenbo,Huang，Qiwei,Mosalam，Hamed,Zhan，Chenchang,Li，Zhiqun,&Pan，Quan.(2022).A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme.IEEE Transactions on Circuits and Systems I: Regular Papers,69(2),634-644.

Xiao，Wenbo,et al."A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme".IEEE Transactions on Circuits and Systems I: Regular Papers 69.2(2022):634-644.