中文版 | English
题名

An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks

作者
通讯作者Wang,Yuhang
DOI
发表日期
2022
ISSN
2153-6961
ISBN
978-1-6654-2136-2
会议录名称
卷号
2022-January
页码
448-453
会议日期
17-20 Jan. 2022
会议地点
Taipei, Taiwan
摘要
Optimized convolutional neural network (CNN) models and energy-efficient hardware design are of great importance in edge-computing applications. The neural architecture search (NAS) methods are employed for CNN model optimization with multi-precision networks. To satisfy the computation requirements, multi-precision convolution accelerators are highly desired. The existing high-precision-split (HPS) designs reduce the additional logics for reconfiguration while resulting in low throughput for low precisions. The low-precision-combination (LPC) designs improve the low-precision throughput with large hardware cost. In this work, a bit-split-and-combination (BSC) systolic accelerator is proposed to overcome the bottlenecks. Firstly, BSC-based multiply-accumulate (MAC) unit is designed to support multi-precision computation operations. Secondly, multi-precision systolic dataflow is developed with improved data-reuse and transmission efficiency. The proposed work is designed by Chisel and synthesized in 28-nm process. The BSC MAC unit achieves maximum 2.40× and 1.64× energy efficiency than HPS and LPC units, respectively. Compared with published accelerator designs Gemmini, Bit-fusion and Bit-serial, the proposed accelerator achieves up to 2.94 × area efficiency and 6.38 × energy-saving performance on the multi-precision VGG-16, ResNet-18 and LeNet-5 benchmarks.
关键词
学校署名
第一 ; 通讯
语种
英语
相关链接[Scopus记录]
收录类别
EI入藏号
20221111785789
EI主题词
Acceleration ; Benchmarking ; Computation theory ; Convolution
EI分类号
Energy Conservation:525.2 ; Information Theory and Signal Processing:716.1 ; Computer Theory, Includes Formal Logic, Automata Theory, Switching Theory, Programming Theory:721.1
Scopus记录号
2-s2.0-85126143003
来源库
Scopus
全文链接https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9712509
引用统计
被引频次[WOS]:0
成果类型会议论文
条目标识符http://sustech.caswiz.com/handle/2SGJ60CL/327841
专题工学院_深港微电子学院
作者单位
School of Microelectronics,Southern University of Science and Technology,Shenzhen,China
第一作者单位深港微电子学院
通讯作者单位深港微电子学院
第一作者的第一单位深港微电子学院
推荐引用方式
GB/T 7714
Dai,Liuyao,Cheng,Quan,Wang,Yuhang,et al. An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks[C],2022:448-453.
条目包含的文件
条目无相关文件。
个性服务
原文链接
推荐该条目
保存到收藏夹
查看访问统计
导出为Endnote文件
导出为Excel格式
导出为Csv格式
Altmetrics Score
谷歌学术
谷歌学术中相似的文章
[Dai,Liuyao]的文章
[Cheng,Quan]的文章
[Wang,Yuhang]的文章
百度学术
百度学术中相似的文章
[Dai,Liuyao]的文章
[Cheng,Quan]的文章
[Wang,Yuhang]的文章
必应学术
必应学术中相似的文章
[Dai,Liuyao]的文章
[Cheng,Quan]的文章
[Wang,Yuhang]的文章
相关权益政策
暂无数据
收藏/分享
所有评论 (0)
[发表评论/异议/意见]
暂无评论

除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。