A 127 nA Quiescent Current Capacitorless NMOS LDO with Fast-Transient Response

Song，Mengjie1,2; Zhan，Chenchang1; Wang，Lidan1; Wu，Litao1; Sun，Bangdong1

10.1109/ICTA53157.2021.9661802

2021

978-1-6654-1748-8

2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021

241-242

24-26 Nov. 2021

Zhuhai, China

In this paper, a fully-on-chip, NMOS low dropout (LDO) regulator with nA quiescent current is proposed. This work combines the dynamic and adaptive current biasing techniques to improve the transient response while maintaining the quiescent current at nA level. The proposed LDO is designed in a 0.18-μm CMOS process and consumes 127 nA quiescent current with 100 mV dropout voltage for generating an output voltage of 800 mV. Furthermore, the output voltage undershoots 215 mv and takes less than 400 ns settling time when the load current steps from 1 μA to 10 mA in 500 ns.

adaptive current bias dynamic current bias fast transient response full-on-chip NMOS LDO ultra-low quiescent current

第一 ; 通讯

英语

EI

20220811683302

Bias voltage ; Power quality ; Transient analysis

Electric Equipment:704.2 ; Electric Power Distribution:706.1.2 ; Electronic Circuits:713 ; Control Equipment:732.1

2-s2.0-85124791602

Scopus

1.Southern University of Science and Technology (SUSTech),School of Microelectronics,Shenzhen,China
2.University Key Laboratory of Advanced Wireless Communications of Guangdong Province,Department of Electrical and Electronic Engineering,SUSTech,Shenzhen,China

Song，Mengjie,Zhan，Chenchang,Wang，Lidan,et al. A 127 nA Quiescent Current Capacitorless NMOS LDO with Fast-Transient Response[C],2021:241-242.