Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching

Counteracting side-channel attacks has become a basic requirement in secure integrated circuits handling physical or sensitive data through cryptography, and preventing information leakage via power and electromagnetic (EM) emissions. Over time, the implementation of protection techniques against power analysis and EM attacks has progressively moved from design-specific (i.e., requiring redesign for their reuse [1]–[3]) to design-reusable frameworks [4]–[10], facilitating reuse with no modifications across designs, system security verification, and reducing the area/power overhead through reuse of existing silicon infrastructure across secure design IPs on the same die. Accordingly, embedding protection into regulators has been extensively explored to degrade the attack SNR and increase the minimum traces to key disclosure (MTD) via current equalization [4], a switching regulator with randomized loop control [5], a digital LDO (DLDO) with noise injection [6], a DLDO with randomized thresholds and AES transformations [7], a DLDO based on an edge-chasing quantizer [8], current-domain signature attenuation [9] and an additional time-varying transfer function [10]. Such protections allow design reuse and some degree of power-security flexibility, but have common limitations in that: 1) they indiscriminately compensate the entire large-signal power rather than focusing on small-signal information-sensitive power contributions, preventing power overhead reductions, 2) the level of protection is set at design time, and cannot improve after chip fabrication (no learning), 3) they cannot adapt to mitigate newly discovered side-channel vulnerabilities and attacks. Indeed, power overhead and security upgrade-ability over time are crucial in energy-autonomous systems with long lifespans and in applications where device replacement is expensive or unfeasible (e.g., IoT, implantables).