A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge

Li，Kai; Zhou，Junzhuo; Wang，Yuhang; Luo，Junyi; Yang，Zhengke; Yang，Shuxin; Mao，Wei; Huang，Mingqiang; Yu，Hao

10.23919/DATE54114.2022.9774679

2022

25th Design, Automation and Test in Europe Conference and Exhibition (DATE)

1530-1591

978-1-6654-9637-7

Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

730-735

14-23 March 2022

Antwerp, Belgium

345 E 47TH ST, NEW YORK, NY 10017 USA

IEEE

Optimized model and energy-efficient hardware are both required for deep neural networks (DNNs) in edge-computing area. Neural architecture search (NAS) methods are employed for DNN model optimization with resulted multi-precision networks. Previous works have proposed low-precision-combination (LPC) and high-precision-split (HPS) methods for multi-precision networks, which are not energy-efficient for precision-scalable vector implementation. In this paper, a bit-split-and-combination (BSC) based vector systolic accelerator is developed for a precision-scalable energy-efficient convolution on edge. The maximum energy efficiency of the proposed BSC vector processing element (PE) is up to 1.95× higher in 2-bit, 4-bit and 8-bit operations when compared with LPC and HPS PEs. Further with NAS optimized multi-precision CNN networks, the averaged energy efficiency of the proposed vector systolic BSC PE array achieves up to 2.18× higher in 2-bit, 4-bit and 8-bit operations than that of LPC and HPS PE arrays.

accelerator bit-split-and-combination CNN NAS Precision-scalable vector systolic

第一

英语

CPCI-S ; EI

Shenzhen Science and Technology Program[KQTD20200820113051096]

Automation & Control Systems ; Computer Science ; Engineering

Automation & Control Systems ; Computer Science, Hardware & Architecture ; Computer Science, Software Engineering ; Engineering, Industrial ; Engineering, Electrical & Electronic

WOS:000819484300140

20222212172784

Deep neural networks ; Energy efficiency ; Systolic arrays

Ergonomics and Human Factors Engineering:461.4 ; Energy Conservation:525.2 ; Algebra:921.1

2-s2.0-85130858962

Scopus

School of Microelectronics,Southern University of Science and Technology,Shenzhen,China

Li，Kai,Zhou，Junzhuo,Wang，Yuhang,et al. A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2022:730-735.