一种全数字锁相环

黄奇伟; 詹陈长

黄奇伟

南方科技大学

南方科技大学

518000 广东省深圳市南山区西丽学苑大道1088号

南方科技大学

518000 广东省深圳市南山区西丽学苑大道1088号 (广东,深圳,南山区)

南方科技大学

518000 广东省深圳市南山区西丽学苑大道1088号 (广东,深圳,南山区)

CN201610593908.7

2016-07-25

CN106301357B

2020-01-07

2020-01-07

授权

2020-01-07

授权发明

第一

本发明公开了一种全数字锁相环包括鉴相模块、数字滤波器、数字控制振荡器和第一分频器；鉴相模块的输出端连接数字滤波器的输入端，用于将鉴相模块第一输入端接收到的参考时钟，与鉴相模块第二输入端接收到的反馈时钟进行相位比较，输出与参考时钟和反馈时钟的相位差呈正相关关系的数字信号；数字滤波器的输出端连接数字控制振荡器的输入端，用于将数字信号滤波后输出至数字控制振荡器，以控制数字控制振荡器以预设频率变化值调节输出时钟的频率，预设频率变化值与数字信号的数值大小正相关。本发明在没有增加锁相环带宽及额外支路的情况下，大幅减小了锁相环的相位锁定时间。

The invention discloses an all-digital phase-locked loop comprising a phase discrimination module, a digital filter, a digitally controlled oscillator and a first frequency divider, wherein an output end of the phase discrimination module is connected with an input end of the digital filter and is used for carrying out phase comparison on a reference clock received by a first input end of the phase discrimination module and a feedback clock received by a second input end of the phase discrimination module and outputting a digital signal in a positive correlation relationship with a phase difference of the reference clock and the feedback clock; and the output end of the digital filter is connected with the input end of the digitally controlled oscillator and is used for outputting the digital signal to the digitally controlled oscillator after filtering the same to control the digitally controlled oscillator to adjust the frequency of an output block via a preset frequency change value, and the preset frequency change value is in positive correlation with the magnitude of the numerical value of the digital signal. The all-digital phase-locked loop disclosed by the invention greatly reduces the phase locking time of the phase-locked loop without increasing the bandwidth or additional branches of the phase-locked loop.

H03L7/085 ; H03L7/18 ; H03L2207/50

H03L7/085 ; H03L7/18

（+PATENT GRANT）[2020-01-07][CN]

1

1

孟金喆 ; 胡彬

北京品源专利代理有限公司

PatSnap

黄奇伟,詹陈长. 一种全数字锁相环[P]. 2020-01-07.