Adaptive Memory-enhanced Time Delay Reservoir and Its Memristive Implementation

Xinming Shi1; Leandro L. Minku2; Xin Yao3

2022

10.1109/TC.2022.3173151

IEEE Transactions on Computers   影响因子和分区

2326-3814

1557-9956

Time Delay Reservoir (TDR) is a hardware-friendly machine learning approach from two perspectives. First, it can prevent the connection overhead of neural networks with increasing neurons. Second, through its dynamic system representation, TDR can also be implemented in hardware by different systems. However, it performs poorly on tasks that involve long-term dependency. In this work, we first introduce a higher-order delay unit, which is capable of accumulating and transferring the long history states in an adaptive manner to further enhance the reservoir memory. Particle Swarm Optimisation is applied to optimize the enhanced degree of memory adaptivity. Our experiments demonstrate its superiority both for short- and long-term memory datasets over seven existing approaches. In light of the hardware-friendly feature of TDR, we further propose a memristive implementation of our adaptive memory-enhanced TDR, where a dynamic memristor and the memristor-based delay element are applied to construct the reservoir. Through circuit simulation, the feasibility of our proposed memristive implementation is verified. The comparisons with different hardware reservoirs show that our proposed memristive implementation is effective both for short- and long-term memory datasets, while exhibiting benefits in terms of smaller circuit area and lower power consumption compared with traditional hardware reservoirs.

Time Delay Reservoir memristor time series prediction

SCI ; EI

英语

其他

Guangdong Provincial Key Laboratory[2020B121201001] ; Program for Guangdong Introducing Innovative and Enterpreneurial Teams[2017ZT07X386] ; Shenzhen Science and Technology Program[KQTD2016112514355531]

Computer Science ; Engineering

Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic

WOS:000866519900007

IEEE COMPUTER SOC

20222012127240

Circuit simulation ; Learning systems ; Neural networks ; Particle swarm optimization (PSO) ; Time delay ; Timing circuits

Electric Network Analysis:703.1.1 ; Electronic Circuits:713 ; Pulse Circuits:713.4 ; Semiconductor Devices and Integrated Circuits:714.2 ; Computer Software, Data Handling and Applications:723 ; Optimization Techniques:921.5

COMPUTER SCIENCE

Web of Science

1.School of Computer Science, University of Birmingham, 1724 Birmingham, Birmingham, United Kingdom of Great Britain and Northern Ireland
2.School of Computer Science, University of Birmingham, Birmingham, Birmingham, United Kingdom of Great Britain and Northern Ireland
3.Computer Science and Engineering, Southern University of Science and Technology, 255310 Shenzhen, Guangdong, China

Xinming Shi,Leandro L. Minku,Xin Yao. Adaptive Memory-enhanced Time Delay Reservoir and Its Memristive Implementation[J]. IEEE Transactions on Computers,2022,PP(99):1-1.

Xinming Shi,Leandro L. Minku,&Xin Yao.(2022).Adaptive Memory-enhanced Time Delay Reservoir and Its Memristive Implementation.IEEE Transactions on Computers,PP(99),1-1.

Xinming Shi,et al."Adaptive Memory-enhanced Time Delay Reservoir and Its Memristive Implementation".IEEE Transactions on Computers PP.99(2022):1-1.