A 65nm 110GOPS 8T-SRAM Computing-in-Memory Macro with Single Cycle Serial Input Mechanism

Shumeng Li1; Tianqi Xu1; Fukun Su1; Xian Tang1; Yupeng Chen2

10.1109/ICCS56666.2022.9936324

2022

978-1-6654-6037-8

2022 IEEE 4th International Conference on Circuits and Systems (ICCS)

33-37

23-26 Sept. 2022

Chengdu, China

This paper presents a high-speed 8T-SRAM computing-in-memory (CIM) macro, which adopts a novel single cycle serial input (SCSI) mechanism and a matching weighted capacitor register circuit, achieving excellent input linearity and calculation speed without input DACs. The register capacitor arrays can be reused by the output SAR ADCs as their four most significant bits (MSBs) DAC capacitors, further improving the area efficiency. The 4kb 8T-SRAM macro supports 4-bit input, 4-bit weight, and 6-bit output, it executes 16 columns of $4b\times 4b$ MAC in parallel, achieving peak throughput of 110.1 GOPS and energy efficiency of 31.4 TOPS/W in 65nm CMOS process.

computing-in-memory SRAM single cycle serial input (SCSI) weighted capacitor array mixed signal computing

其他

IEEE

1.Shenzhen International Graduate School, Tsinghua University, Shenzhen, China
2.School of Microelectronics Southern University of Science and Technology, Shenzhen, China

Shumeng Li,Tianqi Xu,Fukun Su,et al. A 65nm 110GOPS 8T-SRAM Computing-in-Memory Macro with Single Cycle Serial Input Mechanism[C],2022:33-37.