A Hardware-Aware Neural Architecture Search Pareto Front Exploration for In-Memory Computing

Ziyi Guan; Wenyong Zhou; Yuan Ren; Rui Xie; Hao Yu; Ngai Wong

10.1109/ICSICT55466.2022.9963263

2022-10

in Proc. 2020 IEEE 16th Int. Conf. Solid-State and Integrated Circuit Technology (ICSICT)

978-1-6654-6907-4

2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

1-4

2022-10-25

Nanjing

Traditional neural networks deployed on CPU/GPU architectures have achieved impressive results on various AI tasks. However, the growing model sizes and intensive computation have presented stringent challenges for deployment on edge devices with restrictive compute and storage resources. This paper proposes a one-shot training-evaluation framework to solve the neural architecture search (NAS) problem for in-memory computing, targeting the emerging resistive random-access memory (RRAM) analog AI platform. We test inference accuracy and hardware performance of subnets sampled in different dimensions of a pretrained supernet. Experiments show that the proposed one-shot hardware-aware NAS (HW-NAS) framework can effectively explore the Pareto front considering both accuracy and hardware performance, and generate more optimal models via morphing a standard backbone model.

Training Performance evaluation Computational modeling Computer architecture In-memory computing Search problems Hardware

其他

人工提交

1.Southern University of Science and Technology
2.The University of Hong Kong

Ziyi Guan,Wenyong Zhou,Yuan Ren,et al. A Hardware-Aware Neural Architecture Search Pareto Front Exploration for In-Memory Computing[C],2022:1-4.