题名 | Synthesis and implementation of superluminal circuits with zero group delay |
作者 | |
DOI | |
发表日期 | 2018-07-25
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会议录名称 | |
页码 | 1-3
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会议地点 | Xi'an, China
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出版者 | |
摘要 | This paper proposes a novel synthesis and implementation of maximally flat zero group delay (MFZGD) responses for the first time. The proposed synthesis method is more general as one can implement optimized MFZGD filter of any order. It is proved that a lossless network cannot exhibit zero delay response hence loss is necessary for zero group delay. Complete design flow chart with one synthesis example is discussed. The exact agreement between the polynomial and coupling matrix based responses validate the proposed synthesis method. Finally one prototype is fabricated and measured, showing a good agreement between the measured and synthesis responses. |
关键词 | |
学校署名 | 其他
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语种 | 英语
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相关链接 | [Scopus记录] |
收录类别 | |
资助项目 | [S2013050014223]
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EI入藏号 | 20183205677078
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EI主题词 | Delay circuits
; Scattering parameters
; Timing circuits
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EI分类号 | Electric Networks:703.1
; Pulse Circuits:713.4
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Scopus记录号 | 2-s2.0-85051141728
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来源库 | Scopus
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引用统计 |
被引频次[WOS]:0
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成果类型 | 会议论文 |
条目标识符 | http://sustech.caswiz.com/handle/2SGJ60CL/44236 |
专题 | 工学院_电子与电气工程系 |
作者单位 | 1.Electrical Engineering Department, Indian Institute of Technology Bombay, ,India 2.Department of Electrical and Electronics Engineering, SUSTech, ,Shenzhen,China |
推荐引用方式 GB/T 7714 |
Das,Ranjan,Zhang,Qingfeng,Kandwal,Abhishek. Synthesis and implementation of superluminal circuits with zero group delay[C]:Institute of Electrical and Electronics Engineers Inc.,2018:1-3.
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条目包含的文件 | 条目无相关文件。 |
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