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题名

A Chip-Area-Efficient Subthreshold CMOS Voltage Reference with High PSRR Based on Compensated ΔvGS of NMOS Transistors

作者
DOI
发表日期
2018
ISBN
978-1-5386-8241-8
会议录名称
页码
497-500
会议日期
26-30 Oct. 2018
会议地点
Chengdu, China
出版者
摘要
A chip-Area-efficient subthreshold CMOS voltage reference (CVR) with low power consumption and high power supply ripple rejection (PSRR) based on compensated ΔVGS of NMOS transistors is proposed in this paper. The ΔVGS of two different-Vth NMOS transistors is designed to achieve zero temperature coefficient (TC) by compensating its complementary-To-Absolute-Temperature (CTAT) and proportional-To-Absolute-temperature (PTAT) components. An error amplifier driving a current mirror is then used to duplicate the generated zero-TC ΔVGS to a diode-connected NMOS and provide the low-TC VREF. Only two branches are needed in the core part and no resistors are used. Consequently, low power and small area consumptions are achieved with high PSRR. A prototype design is fabricated in a standard 0.18-μm CMOS process. An average TC of 27.26 ppm/°C is measured across 6 dies with a standard derivation of 16.40 ppm/°C over-40 to 80 °C temperature range. The measured line sensitivity is 0.12%/V. The measured PSRR is better than-62.7dB from 10 kHz to 10 MHz. The power consumption is as small as 17.3nW and the chip area is only 0.0244mm2.
© 2018 IEEE.
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学校署名
第一
相关链接[IEEE记录]
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资助项目
Shenzhen Science and Technology Innovation Commission[] ; National Natural Science Foundation of China[61604067] ; National Natural Science Foundation of China[] ; [JCYJ20160530191008447]
EI入藏号
20191006584156
EI主题词
Diode amplifiers ; Electric power utilization ; Energy efficiency ; Temperature ; Voltage measurement
EI分类号
Energy Conservation:525.2 ; Thermodynamics:641.1 ; Electric Power Systems:706.1 ; Amplifiers:713.1 ; Semiconductor Devices and Integrated Circuits:714.2 ; Electric Variables Measurements:942.2
来源库
EV Compendex
全文链接https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8605633
引用统计
被引频次[WOS]:0
成果类型会议论文
条目标识符http://sustech.caswiz.com/handle/2SGJ60CL/50971
专题南方科技大学
工学院_深港微电子学院
作者单位
Department of EEE, Southern University of Science and Technology (SUSTech), Shenzhen, China
第一作者单位南方科技大学
第一作者的第一单位南方科技大学
推荐引用方式
GB/T 7714
Lei, Yu,Zhan, Chenchang,Huang, Chenyu,et al. A Chip-Area-Efficient Subthreshold CMOS Voltage Reference with High PSRR Based on Compensated ΔvGS of NMOS Transistors[C]:Institute of Electrical and Electronics Engineers Inc.,2018:497-500.
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