高频GaN驱动芯片关键模块设计

电动汽车及5G技术的高速发展，使得高频、高效率、高压以及小型化的电源电压转换器的需求量激增，电源电压转换的要求也随之提高。传统的硅基器件难以满足现实需求，氮化镓（GaN）器件与传统硅基器件相比，具有高速、耐压高、低导通阻抗和小寄生电容的优势，能够与高频、高效率、高压的应用场景相适配。

本文基于汽车电子和数据中心等电压转换背景，设计了开环的GaN驱动电路。开环GaN驱动电路的主要设计模块包括片内自举电路、可控制的死区时间调控模块以及高速高抗扰度的电平位移电路。对于GaN驱动电路的核心模块电平位移电路进行了着重设计，采用了电容耦合的多级交叉结构以提升电路的传输速度和dV/dt抗扰度。将所设计的电平位移电路与文献中适用于高速、高频、高压的电平位移电路进行比对。在输入电压为48V，开关频率为10MHz的工作环境中，仿真证明本文所设计的电平位移电路具有最低的传输延时，最低传输延时为450ps，具有200V/ns的dV/dt抗扰度和0.07ns的传输延时失配，静态电流为0.14μA。本设计基于0.18μm CMOS BCD的工艺，实现了1.8mm²的开环GaN驱动电路。经过测试本文所提出的电平位移电路最小传输延时仅为600ps，同时具有的版图面积为0.0085mm²，均低于引用文献中电平位移电路的性能指标。

本文对于GaN驱动电路同时完成了闭环回路的实现，通过PWM模式下的电压控制方式实现了电压从48V到12V的转换，利用Type-II的补偿方式实现了电路的稳定。仿真结果表明在12V输出条件下，电压输出纹波约为24mV。在负载瞬态仿真中，当输出电流从300mA到3A的相互转换过程中，其下冲电压为169mV，下冲电压的恢复时间约为3.19μs。过冲电压为146mV，过程电压的恢复时间约为3.54μs。在5MHz的工作频率下，负载电流从300mA到3A的仿真过程中，其最低效率为负载电流300mA情况下，效率为83.1%。峰值效率为负载电流在2.4A的情况下，效率为95.2%。

With the rapid development of automotive and 5G technology, the demand for high-frequency, high-efficiency, high-voltage, and miniaturized power voltage converters has increased significantly, and the requirements for power voltage conversion have also increased accordingly. Traditional silicon-based devices are unable to meet the current needs, whereas Gallium Nitride (GaN) devices have advantages over traditional silicon-based devices in terms of high speed, high voltage resistance, low on-resistance, and small parasitic capacitance, making them suitable for high-frequency, high-efficiency, and high-voltage applications.

Based on the background of voltage conversion in automotive electronics and data centers, this article presents an open-loop GaN driver circuit design. The main design modules of the open-loop GaN driver circuit include an on-chip bootstrap circuit, a controllable dead-time control module, and a high-speed, high-immunity level shift circuit. The core module of the GaN driver circuit, the level shift circuit, is designed with a capacitively coupled multi-stage cross structure to improve the circuit's transmission speed and dV/dt immunity. The designed level shift circuit is compared with a level shift circuit in literature suitable for high-speed, high-frequency, and high-voltage applications. The simulation results demonstrate that the level shift circuit designed in this article has the lowest transmission delay, with a minimum delay of 450ps, 200V/ns dV/dt immunity, 0.07ns delay mismatch, and a static current of 0.14μA. This design is based on the 0.18μm CMOS BCD process and has achieved an open-loop GaN driver circuit size of 1.8mm2. After testing, the minimum transmission delay of the level shift circuit proposed in this article is only 600ps, and the layout area is 0.0085mm2, which is lower than the performance indicators of the level shift circuit in the reference literature.

This article also achieves closed-loop feedback for the GaN driver circuit, realizing voltage conversion from 48V to 12V through voltage control in PWM mode, and using Type-II compensation to stabilize the circuit. The simulation results show that under the 12V output condition, the voltage output ripple is approximately 24mV. In the transient simulation of the load, when the output current switches from 300mA to 3A, the undershoot voltage is 169mV, and the recovery time of the undershoot voltage is approximately 3.19μs. The overshoot voltage is 146mV, and the recovery time of the overshoot voltage is approximately 3.54μs. At a working frequency of 5MHz, the lowest efficiency during the simulation process of the load current switching from 300mA to 3A is 83.1% under the load current of 300mA, and the peak efficiency is 95.2% when the load current is 2.4A.

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