CMOS 全集成光接收机前端芯片的研究

信息技术的发展推动了数据中心流量的持续增长和对高速通信系统的性能需求。相比电缆和无线通信，光通信具有高带宽、高安全性、低功耗和低干扰的优势。而传统的光通信接收机由于封装导致的严重电磁干扰， 且分立的光电转换器件成本过高，难以大规模部署在数据中心内部。基于 标准 CMOS 工艺的全集成光通信接收机能够最大程度地减小封装造成的限制，降低光电器件成本，具有十分广阔的研究意义和商业价值。

本文基于 28 nm CMOS 工艺，研究设计了光接收机前端，包括 CMOS 光电探测器、跨阻放大器电路、单端转差分电路和直流失调消除电路。提出了一种水平 p-well/n-well 结构的光电探测器，使用 DNW 区域消除标准 CMOS 工艺中 P 型衬底引入的缓慢衬底扩散电流，利用 p-well 和 n-well 形成插指结构的水平 PN 结，提高激光吸收效率，降低载流子渡越时间，提升光电探测器带宽。设计了基于反相器架构的三级跨阻放大器电路，将光电探测器输出的电流信号转换为电压信号，同时利用前馈相加的连续时间线性均衡技术拓展带宽，通过反相器片选调整跨阻增益。后续的单端转差分电路将跨阻放大器输出的单端信号转为差分信号，同时利用有源电感进行带宽拓展。直流失调消除电路通过负反馈的方式调整跨阻放大器的输入电流，抑制输出端直流电平的失调。

测试结果表明 CMOS 光电探测器带宽可达 4.2 GHz，响应度为 0.13 A/W。 根据测试结果对光电探测器进行建模，探测器模型和光接收机前端电路联合后仿真结果表明，CMOS 全集成光接收机前端芯片带宽达到了 9 GHz，跨 阻增益为 72 dBΩ。本文首次在 CMOS 全集成光接收机前端芯片中验证了 PAM-4 信号的传输，实现了 30 Gb/s PAM-4 信号的眼图张开。芯片能耗仅为 0.83 pJ/bit，版图面积为 0.64 mm2 。

The development of information technology has driven the continued growth of data center traffic and the performance demand of high-speed communication systems. Compared to electric cable communication and wireless communication, optical communication offers the advantages of high bandwidth, high security, low power consumption and low interference. Traditional optical communication receivers are difficult to deploy inside data centers on a large scale due to expensive optoelectronic conversion devices and electromagnetic interference caused by packaging. Fully integrated optical communication receivers based on standard CMOS processes can minimize the cost and packaging impact and have research significance and commercial value.

This thesis investigates and designs an optical receiver front-end based on 28 nm CMOS process, including a CMOS photodetector, a transimpedance amplifier circuit, a single-ended-to-differential circuit, and a DC offset cancellation circuit. This thesis proposes a horizontal p-well/n-well structure photodetector based on 28 nm CMOS process, using the DNW region to eliminate the slow substrate diffusion current introduced by the P-type substrate in the standard CMOS process, and using the p-well and n-well to form a horizontal PN junction with an inserted finger structure to improve the laser absorption efficiency, reduce the carrier crossing time, and enhance the photodetector bandwidth. The three-stage inverter based transimpedance amplifier circuit converts the current signal from the photodetector output into a voltage signal, while expanding the bandwidth by using the continuous-time linear equalization technique of feed-forward summation, adjusting the transimpedance gain by inverter slides selection. The subsequent single-ended to differential circuit converts the single-ended signal from the transimpedance amplifier into a differential signal, while using an active inductor for bandwidth expansion. The DC offset cancellation circuit adjusts the input current of the transimpedance amplifier by negative feedback to suppress the DC offset at the output.

Test results show that the proposed CMOS photodetector can reach a bandwidth of 4.2 GHz and a responsivity of 0.13 A/W. Modeling photodetectors based on test results, the post-simulation results show that the CMOS fully integrated optical receiver front-end has a bandwidth of 9 GHz and a transimpedance gain of 72 dBΩ. This thesis first verifies the transmission of PAM-4 signals in the CMOS fully integrated optical receiver front-end chip, achieving eye diagram opening of 30 Gb/s PAM-4 signals. The chip energy consumption is only 0.83 pJ/bit, and the chip layout area is 0.64 mm2.

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