氧化物忆阻器器件制备与性能优化

  面向人工神经网络的计算场景，以数字逻辑门电路为运算载体的、基于冯诺依曼计算架构的处理器已经可以准确且高效地完成任务。但传统计算架构中存储与计算的功能由两个各自独立的模块实现，模块间数据的反复读写与传输会产生非必要的功耗并增加延时。而在基于忆阻器的存算一体架构中，乘法与累加运算可以在存储单元原位进行，这样的系统省去了部分数据的传输，有利于提高神经网络计算的能耗比。本文面向存算一体系统对忆阻器的性能需求，通过设计器件结构与研究制备工艺实现对HfO_x忆阻器性能的优化。

  本文首先依据忆阻器的阻变原理探索了一套性能测试流程，包括从直流阻变特性中获取后续脉冲测试的参数，以及以脉冲调节电导为基础进行器件稳定性的实验，为本文中对氧化物忆阻器器件的性能测试与优化奠定基础。基于这一测试方法，探究了HfO_x忆阻器的材料选择与器件制备工艺。对于Ti/Pt/HfO_x/Ti/Pt结构的忆阻器，发现原子层沉积生长的HfO_x最优厚度为5 nm，HfO_x上方Ti层厚度应当为10 nm，这一结构的器件在N₂气氛下300℃退火1 min后表现出50倍的开关比，且在50次循环后仍保持稳定的阻变特性。通过进一步脉冲测试证明这一器件具有良好的电导逐脉冲调节特性、保持性、周期间变化以及高温稳定性等性能，展现了其在存算一体系统中的应用潜力。为了克服HfO_x忆阻器低电导向高电导状态转变时的突变情况，以及降低忆阻器的工作电流，探索了TiN/HfO_x/TaO_x/TiN结构器件的制备工艺。发现Ti靶与N₂反应溅射制备的TiN适宜作为器件电极。通过比较使用Ta靶在O₂中反应溅射与使用Ta₂O₅靶射频溅射得到的两种TaO_x构成的忆阻器，发现HfO_x忆阻器中反应溅射制备的缺氧TaO_x对器件表现阻变特性具有决定性作用。

  此外，为了缓解忆阻器存算一体系统对器件与电路要求严苛的状况，一种将神经网络权值数据按二进制位分片存入多个忆阻器器件的配置策略被提出。本文在性能出色的HfO_x忆阻器阵列上模拟通过这一策略实现乘法运算的过程，揭示了该策略在器件层面部署的可能性与未来发展的潜力。

  Toward the computing scenarios of artificial neural networks, processors based on von Neumann’s computing architecture, which utilize digital logic gate circuits can already complete tasks accurately and efficiently. However, in the traditional computing architecture, the functions of storage and computing are implemented by two independent modules, and transmission of data between modules will generate power consumption and serious delay. In the Computing-in-memory architecture based on memristors, the multiplication and accumulation can be performed in situ in the storage unit. Such a system reduces data transmission, which improves the efficiency of neural network computing.

  This paper first explores a set of performance test procedures based on the resistive principle of memristors, including designing the parameters of pulse tests referring to the DC voltage sweeping characteristics, and device stability experiments based on pulse-adjusted conductance. For memristors with Ti/Pt/HfO_x/Ti/Pt structure, it is found that the optimal thickness of HfO_x fabricated by atomic layer deposition is 5 nm, and the thickness of the Ti layer above HfO_x should be 10 nm. The device with this structure is annealed at 300℃ for 60 s in N₂ atmosphere, and it exhibits 50 times on-off ratio and maintains stable resistive characteristics after 50 cycles. Further pulse tests prove that this device has good conductance pulse-by-pulse adjustment characteristics, retention, cycle-to-cycle variation, and high-temperature stability, which demonstrates its application potential in Computing-in-memory systems. In order to overcome the abrupt switching of HfO_x memristors from low conductance to high conductance states and reduce the working current of memristors, the fabrication process of TiN/HfO_x/TaO_x/TiN structure devices was explored. It is found that TiN deposited by reactive sputtering of the Ti target in N₂ is suitable as an electrode. By comparing the two kinds of TaO_x memristors obtained by reactive sputtering of the Ta target in O₂ and RF sputtering of the Ta₂O₅ target, it is found that the oxygen-deficient TaO_x fabricated by reactive sputtering has a decisive effect on the resistive switching characteristics of HfO_x memristors.

  Furthermore, for relieving strict requirements of device performance and periphery circuits, a configuration strategy of neural network weight data into multiple memristor devices is proposed. This paper also simulates the process of multiplication by this strategy on a memristor array, revealing the possibility and potential of its deployment at the device level.

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