扇出型晶圆级封装的翘曲分析及控制方法

扇出型晶圆级封装(Fan-Out Wafer Level Packaging, FOWLP)是先进电子封装技术的重要组成部分。相较于传统封装，FOWLP在封装厚度、制造成本、电气性能和使用功耗等方面都有较强的优势。FOWLP采用了将硅芯片阵列嵌入环氧塑封料的方法，有效扩展了芯片封装面积，从而支持更多的引脚数量。考虑到FOWLP的技术优势以及对市场前景的预测，FOWLP有希望成为下一代便携式移动设备芯片首选的先进封装技术。然而，由于封装结构、材料特性和工艺条件等多重因素的耦合，FOWLP的应用面临着明显的翘曲问题，严重影响芯片良率与可靠性。为了提高工艺过程的良品率和电子芯片的使用寿命，开发一种适用于FOWLP的可靠性评估方法来优化封装设计和材料是有必要的。

本文以FOWLP作为研究对象，以有限元法和实验测试作为研究方法，系统性地研究了封装工艺过程中的翘曲实时演化规律。基于粘弹性材料理论，在仿真过程中充分考虑了封装结构、材料性能、工艺条件等因素，对扇出型封装的翘曲产生机理进行了阐释，并提出了能够有效控制晶圆翘曲值的解决方案。结果表明，在结构设计方面，通过减小扇出比、减小芯片研磨厚度或者选择合适的塑封厚度与金属层厚度能够减小晶圆的翘曲值。在材料性能和工艺条件方面，使用杨氏模量较低和热膨胀系数较小的塑封材料和介电材料，或者降低固化温度，都能够有效控制翘曲值。此外，针对晶圆的非对称翘曲现象，提出了假片替换法和芯片间隔排列法，在不改变扇出比的前提下优化芯片布局方式，使翘曲值下降率达到了47.29%，改善翘曲形态的同时能够大幅度减小翘曲值。

Fan-Out Wafer Level Packaging (FOWLP) is an important component of advanced electronic packaging technology. Compared with traditional packaging, FOWLP has strong advantages in packaging thickness, manufacturing costs, electrical performance, and power consumption. FOWLP uses the method of embedding silicon chip array into molding compound, which effectively expands the packaging area and supports more pins. Considering the technical advantages of FOWLP and market forecast, FOWLP has the potential to become a preferred packaging technology for the next generation of portable mobile device chips. However, due to the coupling of multiple factors such as packaging structure, material properties, and process conditions, the application of FOWLP faces significant warpage problems, which seriously affect chip yield and reliability. To improve the yield of the process and the service life of electronic chips, it is necessary to develop a reliability evaluation method suitable for FOWLP to optimize package design and materials.

In this thesis, FOWLP is taken as the research object, the finite element method and experimental test are used as research methods, and the real-time evolution of warpage during the packaging process is systematically studied. Based on the theory of viscoelastic material, the simulation process fully considers the packaging structure, material properties, process conditions, and other factors, explains the warpage mechanism in the process of FOWLP, and a solution that can effectively control the wafer warpage value was proposed. Results showed that in terms of structural design, the warpage value can be reduced by reducing the fan-out ratio, reducing the grinding thickness of chip, or selecting the appropriate thickness of molding compound and metal layer. In terms of material properties and process conditions, using molding compound and dielectric materials with low Young's modulus and small coefficient of thermal expansion, or reducing the curing temperature can effectively control the warpage value. Furthermore, to solve the asymmetric warpage phenomenon of the reconstituted wafer, the dummy replacement method and the interval arrangement method were proposed to optimize the chip layout without changing the fan-out ratio, resulting in a 47.29% decrease in the warpage value, which can greatly reduce the warpage value while improving the warpage morphology.

[1] 陈志文, 梅云辉, 刘胜, 等. 电子封装可靠性: 过去, 现在及未来[J]. 机械工程学报, 2021, 57(16): 248-268.
[2] VENKATA N C Y, VENU K N. Parametric Study of Thermally Induced Warpage of FpBGA Package Using Finite Element Methods[J]. Materials Today: Proceedings, 2021, 51: 430-434.
[3] ZHANG S Y, LI Z F, ZHOU H Z, et al. Challenges and Recent Prospectives of 3D Heterogeneous Integration[J]. e-Prime - Advances in Electrical Engineering, Electronics and Energy, 2022, 2: 100052.
[4] MOORE G E. Cramming More Components onto Integrated Circuits[J]. Electronics, 1965, 38(8): 114-117.
[5] MACK C A . Fifty Years of Moore's Law[J]. IEEE Transactions on Semiconductor Manufacturing, 2011, 24(2): 202-207.
[6] 曹立强, 侯峰泽, 王启东, 等. 先进封装技术的发展与机遇[J]. 前瞻科技, 2022, 1(3): 101-114.
[7] 李杨, 蔡绪峰, 王剑峰, 等. 多层堆叠扇出型集成热仿真分析及优化[J]. 中国集成电路, 2022, 31(8): 1-6.
[8] 王龙兴. 2019年中国集成电路封装测试业的状况[J]. 集成电路应用, 2020, 37(04): 1-3.
[9] 郭昌宏, 李习周. 扇出型晶圆级封装技术及其在移动设备中的应用[J]. 电子工业专用设备, 2018, 47(5): 1-4.
[10] 吉勇, 王成迁, 李杨. 扇出型封装发展、挑战和机遇[J]. 电子与封装, 2020, 20(08): 3-8.
[11] BRUNNBAUER M, FURGUT E, BEER G, et al. An Embedded Device Technology Based on A Molded Reconfigured Wafer[C]// 2006 56th Electronic Components and Technology Conference (ECTC), IEEE, 2006: 1-5.
[12] KESER B, AMRINE C, DUONG T, et al. The Redistributed Chip Package: A Breakthrough for Advanced Packaging[C]// 2007 57th Electronic Components and Technology Conference (ECTC), IEEE, 2007: 286-291.
[13] TSENG C F, LIU C S, WU C H, et al. InFO (Wafer Level Integrated Fan-Out) Technology[C]// 2016 66th Electronic Components and Technology Conference (ECTC),IEEE, 2016: 1-6.
[14] LAU J H. Fan-out Wafer-Level Packaging for 3D IC Heterogeneous Integration[C]// 2018 China Semiconductor Technology International Conference (CSTIC), 2018: 1-6.
[15] TSAI C H, LIU S W, CHIANG K N. Warpage Analysis of Fan-Out Panel-Level Packaging Using Equivalent CTE[J]. IEEE Transactions on Device and Materials Reliability, 2020, 20(1): 51-57.
[16] LAU J H, LI M, TIAN D, et al. Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2017, 7(10): 1729-1738.
[17] KANAJI K, MIZUIKE K, NISHIGUCHI T. High Performance Liquid Epoxy Encapsulant for Advanced Semiconductor Package[C]// 1997 1st Electronic Packaging Technology Conference (EPTC), IEEE, 1997: 215-218.
[18] SHAM M L, KIM J K. Evolution of Residual Stresses in Modified Epoxy Resins for Electronic Packaging Applications[J]. Composites Part A: Applied Science and Manufacturing, 2004, 35(5): 537-546.
[19] NIU L, YANG D, ZHANG G Q. Characterization, Modelling, and Parameter Sensitivity Study on Electronic Packaging Polymers[C]// 2009 International Conference on Electronic Packaging Technology & High Density Packaging, IEEE, 2009: 763-767.
[20] SADEGHINIA M, JANSEN K M B, ERNST L J. Characterization and Modeling the Thermo-mechanical Cure-dependent Properties of Epoxy Molding Compound[J]. International Journal of Adhesion and Adhesives, 2012, 32: 82-88.
[21] KAN K, OI Y, FUJII Y, et al. The Novel Liquid Molding Compound for Fan-out Wafer Level Package[C]// 2016 International Conference on Electronics Packaging (ICEP), IEEE, 2016: 557-561.
[22] KWON K, LEE Y, KIM J, et al. Compression Molding Encapsulants for Wafer-Level Embedded Active Devices: Wafer Warpage Control by Epoxy Molding Compounds[C]// 2017 67th Electronic Components and Technology Conference (ECTC), IEEE, 2017: 319-323.
[23] UENO K, DOHI K, MURANAKA K, et al. Development of Liquid, Granule and Sheet Type Epoxy Molding Compounds for Fan Out Wafer Level Package[C]// 2017 67th Electronic Components and Technology Conference (ECTC), IEEE, 2017: 285-291.
[24] OI Y, FUJII Y, HIRAOKA T, et al. Warpage Control of Liquid Molding Compound for Fan-Out Wafer Level Packaging[C]// 2018 68th Electronic Components and Technology Conference (ECTC), IEEE, 2018: 967-972.
[25] WANG X, ANDRIANI Y, LIU S, et al. Dynamic Mechanical Analysis and Viscoelastic Behavior of Epoxy Molding Compounds Used in Fan-Out Wafer-Level Packaging[C]// 20th Electronics Packaging Technology Conference (EPTC), IEEE, 2018: 585-590.
[26] CHAO J, ZHANG R, DO T, et al. Low Warpage Liquid Compression Molding (LCM) Material for High Density Fan-out and Wafer Level Packaging Applications[C]// 70th Electronic Components and Technology Conference (ECTC), IEEE, 2020: 924-930.
[27] ALMEIDA R, BARROS I, CAMPOS J, et al. Enabling of Fan-Out WLP for More Demanding Applications by Introduction of Enhanced Dielectric Material for Higher Reliability[C]// 2014 64th Electronic Components and Technology Conference (ECTC), IEEE, 2014: 935-939.
[28] ZHU C, NING W, XU G, et al. Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage[J]. Journal of Electronic Materials, 2014, 43(9): 3255-3262.
[29] IKEHIRA S. Novel Insulation Materials Suitable for FOWLP and FOPLP[C]// 71st Electronic Components and Technology Conference (ECTC), IEEE, 2021: 729-735.
[30] KIANG B, WITTMERSHAUS J, KAR R, et al. Package Warpage Evaluation for Multi-Layer Molded PQFP[C]// 1991 17th International Electronics Manufacturing Technology Symposium, IEEE, 1991: 89-93.
[31] SRIKANTH N. Warpage Analysis of Epoxy Molded Packages Using Viscoelastic Based Model[J]. Journal of Materials Science, 2006, 41(12): 3773-3780.
[32] HWANG S J, CHANG Y S. P-V-T-C equation for epoxy molding compound[J]. IEEE Transactions on Components and Packaging Technologies, 2006, 29(1): 112-117.
[33] DENG S S, HWANG S J, LEE H H. Warpage Prediction and Experiments of Fan-Out Wafer level Package During Encapsulation Process[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2013, 3(3): 452-458.
[34] ZHU C S, GUO P F, DAI Z B. Investigation on Wafer Warpage Evolution and Wafer Asymmetric Deformation in Fan-Out Wafer Level Packaging Processes[C]// 2017 18th International Conference on Electronic Packaging Technology (ICEPT), IEEE, 2017: 664-668.
[35] CHIU T C, YEH E Y. Warpage Simulation for the Reconstituted Wafer Used in Fan-Out Wafer Level Packaging[J]. Microelectronics Reliability, 2018, 80: 14-23.
[36] CHEN Z, ZHANG X, LIM S P S, et al. Wafer Level Warpage Modelling and Validation for FOWLP Considering Effects of Viscoelastic Material Properties Under Process Loadings[C]// 2019 69th Electronic Components and Technology Conference (ECTC), IEEE, 2019: 1543-1549.
[37] WU M L, LAN J S. Simulation and Experimental Study of the Warpage of Fan-Out Wafer-Level Packaging: The Effect of the Manufacturing Process and Optimal Design[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2019, 9(7): 1396-1405.
[38] SALAHOUELHADJ A, GONZALEZ M, VANSTREELS K, et al. Study of Wafer Warpage for Fan-Out Wafer Level Packaging: Finite Element Modelling and Experimental Validation[C]// 2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), IEEE, 2019: 1-7.
[39] CHENG H C, LIU Y C. Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging[J]. Journal of Electronic Packaging, 2020, 142(1): 42-51
[40] JI L, CHAI T C, SEE G, et al. Modelling and Prediction on Process Dependent Wafer Warpage for FOWLP Technology Using Finite Element Analysis and Statistical Approach[C]// 2020 22nd Electronics Packaging Technology Conference (EPTC), IEEE, 2020: 386-393.
[41] WANG S, SUN Y, SHENG C, et al. Warpage Analysis and Prediction of the Advanced Fan-Out Technology Based on Process Mechanics[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2021, 11(12): 2201-2213.
[42] BRAUN T, BECKER K F, VOGES S, et al. Challenges and Opportunities for Fan-Out Panel Level Packing (FOPLP)[C]// 2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), IEEE, 2014: 154-157.
[43] HOU F Z, LIN T Y, CAO L Q, et al. Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2017, 7(10): 1721-1728.
[44] LAU J H, LI M, LI Q M, et al. Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2018, 8(6): 991-1002.
[45] BRAUN T, RAATZ S, MAASS U, et al. Development of a Multi-project Fan-Out Wafer Level Packaging Platform[C]// 2017 67th Electronic Components and Technology Conference (ECTC), IEEE, 2017: 1-7.
[46] BRAUN T, BECKER K F, HOELCK O, et al. Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration[J]. Micromachines, 2019, 10(5)
[47] MOTOHASHI N, KIMURA T, MINEO K, et al. System in Wafer-Level Package Technology with RDL-first Process[C]// 2011 61st Electronic Components and Technology Conference (ECTC), IEEE, 2011: 59-64.
[48] COURANT R. Variational Methods for the Solution of Problems of Equilibrium and Vibrations[J]. Bulletin of the American Mathematical Society, 1943, 49(1): 1-23.
[49] TURNER M J. A Method of Finite Element Analysis for Structural Frames[J]. Journal of Aeronautical Sciences, 1956, 23(9): 805-827.
[50] CLOUGH. The Finite Element Method in Plane Stress Analysis[C]// 2nd ASCE Conference on Electronic Computation, 1960: 345-378.
[51] 陈锡栋, 杨婕, 赵晓栋, 等. 有限元法的发展现状及应用[J]. 中国制造业信息化,2010,39(11): 6-8.
[52] 杜平安. 有限元网格划分的基本原则[J]. 机械设计与制造,2000(01): 34-36.
[53] 张玉峰, 朱以文, 丁宇明. 有限元分析系统ABAQUS中的特征技术[J]. 工程图学学报, 2006(05): 142-148.
[54] 王璐, 肖潇, 李刚, 等. IC封装环氧塑封料用商业化环氧树脂与酚醛固化剂的研究进展[J]. 精细与专用化学品,2022,30(04): 1-9.
[55] 张未浩, 丁全青, 胡红霞. 不同环氧树脂对EMC性能的影响[J]. 中国集成电路,2018,27(11): 58-62.
[56] 王征, 吴若峰. 基于MATLAB/SIMULINK的聚合物动态力学松弛的仿真研究[J]. 计算机仿真,2003(03): 104-107.
[57] PACHECO J E L, BAVASTRI C A, PEREIRA J T. Viscoelastic Relaxation Modulus Characterization Using Prony Series[J]. Latin American Journal of Solids and Structures, 2015, 12(2): 420-446.
[58] 乌云其其格, 马连勇, 李峰, 等. 高温固化环氧树脂芳纶复合材料性能研究[J]. 高科技纤维与应用,2020,45(06): 17-22.
[59] LI R Z. Time-Temperature Superposition Method for Glass Transition Temperature of Plastic Materials[J]. Materials Science and Engineering: A, 2000, 278(1): 36-45.
[60] Williams M L, Landel R F, Ferry J D. The Temperature Dependence of Relaxation Mechanism in Amorphous Polymers and Other Glass Forming Liquid[J]. Journal of the American Chemical Society, 1955, 77(14): 3701-3707.
[61] Celina M, Gillen K T, Assink R A. Accelerated Aging and Lifetime Prediction: Review of Non-Arrhenius Behaviour Due to Two Competing Processes[J]. Polymer Degradation and Stability, 2005, 90(3): 395-404.
[62] WANG T, LI J, NIU F, et al. Low-temperature curable and low-dielectric polyimide nanocomposites using aminoquinoline-functionalized graphene oxide Nanosheets[J]. Composites Part B: Engineering, 2022, 228: 109412.