DESIGN AND ANALYSIS OF LOW-POWER VOLTAGE REFERENCES AND LINEAR REG ULATORS FOR IOT APPLICATIONS

The development of IoT has been driven by 5G communication, and power management chips have been widely used in the wireless nodes of IoT due to their ability to transform, distribute, and manage electrical en￾ergy. Power management chips mainly include voltage references, linear regulators, and switching regulators. This thesis focuses on two types of circuits: voltage references and linear regulators. For voltage references, in order to meet the requirements of IoT applications, reducing voltage and power consumption has always been the main research direction, which has also led to the continuous iteration of different topologies. The operating voltage of the full-CMOS voltage reference can be lower than that of the bandgap voltage reference. Furthermore, full-CMOS voltage reference consumes less power than bandgap voltage reference, making it more suitable for wireless sensor networks. Therefore, the research work of this thesis focuses on the innovation of the full-CMOS voltage reference topology. As for linear regulators, they are mainly classified into two types: classical operational amplifier resistor feedback architecture and flipped voltage follower architecture. A great deal of research has focused on reducing quiescent current while improving transient response. Because reducing current can cause a slowing down of transient response, achieving fast transient response at low current has always been a technical obstacle,which has been widely studied. Currently, there are two approaches to achieving improvement: one is to add auxiliary circuits, and the other is to innovate the topology. This thesis has made circuit innovations in both of these areas.The main focus of this thesis is to propose six chip designs based on the application requirements in different scenarios of IoT. The proposed circuits not only have application value but also provide guidance for de￾sign methods. The following is an overview of the six designs. The first chip design is a 0.3 V voltage reference. This design has the advantage of low-voltage operation by utilizing extra self-bulk-bias. Additionally, because this circuit is based on the derived topology of the classical three-transistor voltage reference and the negative feedback loop introduced by the self-bulk-bias can stabilize the output voltage, the proposed voltage reference has excellent line sensitivity (0.1%/V). These fea￾tures make this chip design applicable to energy harvesting and wireless earphones in outdoor environments.The second chip design is a voltage reference with 0.25 V supply. This chip design has three advantages. Firstly, it utilizes the leakage current generated by the PMOS transistor operating in the cut-off region to bias the circuit, resulting in ultra-low-current consumption. Secondly, the cas￾caded structure can provide low-impedance nodes for the second-stage core circuit, achieving the goal of low-voltage operation for the chip.
Thirdly, by replacing the traditional NMOS transistor with a PMOS tran￾sistor and using the reverse current generated by the bulk diode in the CMOS technology for temperature compensation, the temperature range of this chip is broadened. This chip can be used in indoor IoT devices where stable conditions ensure reliable supply, and its inherent characteristics of low-voltage and low-power consumption can extend the battery life.The third chip design is a voltage reference designed to operate below 0.2 V. It improves the accuracy of the output voltage by utilizing transistors of the same type with similar threshold voltage variation trends across process corners. The proposed topology can provide high-precision reference voltage without the need for trimming circuits. Moreover, by avoiding the use of special transistors, the number of mask layers has also been reduced, thereby reducing costs and maintaining process compatibility.
This circuit can be employed in high-precision chips, including ultra-low￾power analog-to-digital converters.The fourth chip design is a linear regulator with high current-area efficiency and fast transient response. It can operate with less than 1 μA quiescent current, and occupy an area of only 8771 μm2 . This design is mainly used for system integration because of its small area, low-power consumption, and ability to isolate capacitors and inductors on the PCB.
The fifth chip design is an NMOS linear regulator that does not require adaptive biasing. During static standby mode and dynamic re[1]sponse, the proposed design maintains a current consumption level of ap[1]proximately 100 nA, thus further extending the use time of IoT devices. A controllable switch integrated with a charge pump allows the circuit to turn off the charge pump under dual supply conditions, which further im[1]proves the load transient response.

The sixth chip design is a hybrid topology that unifies the functions of a voltage reference and a linear regulator. This is achieved by incorpo[1]rating the driving transistor of the traditional linear regulator into the voltage reference and introducing negative feedback loop. This design is capable of providing a stable reference voltage that remains unaffected by variations in process, temperature, and power supply, while also driving load currents. By adopting a hybrid architecture, this design further improves its power-area efficiency and facilitates higher chip integration.

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