题名 | RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate |
作者 | |
DOI | |
发表日期 | 2023
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ISSN | 2834-9830
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ISBN | 979-8-3503-3268-1
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会议录名称 | |
页码 | 1-5
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会议日期 | 11-13 June 2023
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会议地点 | Hangzhou, China
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摘要 | Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which can effectively improve the computing efficiency of the convolutional neural network (CNN). To improve throughput and computational energy efficiency while maintaining accuracy, this paper proposes an SRAM CIM accelerator with the capacitor-coupling method. Charge-domain based accumulation scheme can reduce the impact of multiplication and accumulation (MAC) unit variations, which makes it possible to increase computational throughput and energy efficiency in a fully-parallel manner. Furthermore, the array size and the mapping of weights are designed to improve the utilization by considering the network characteristics and data volume. At the data flow level, this paper proposes a novel data reuse scheme to make full use of the input data. Besides, design-specific custom instructions based on RISC-V are designed to improve data transfer efficiency. Simulation results show that the proposed SRAM-based accelerator can achieve energy efficiency of 284.7, 71.2, and 17.8 TOPS/W at 2-bit, 4-bit, and 8-bit modes in 28-nm CMOS. |
关键词 | |
学校署名 | 第一
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相关链接 | [IEEE记录] |
收录类别 | |
EI入藏号 | 20233114469024
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EI主题词 | Computational efficiency
; Convolutional neural networks
; Data transfer
; Energy efficiency
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EI分类号 | Energy Conservation:525.2
; Data Storage, Equipment and Techniques:722.1
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来源库 | IEEE
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全文链接 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10168630 |
引用统计 |
被引频次[WOS]:0
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成果类型 | 会议论文 |
条目标识符 | http://sustech.caswiz.com/handle/2SGJ60CL/548971 |
专题 | 南方科技大学 |
作者单位 | Southern University of Science and Technology, Shenzhen, China |
第一作者单位 | 南方科技大学 |
第一作者的第一单位 | 南方科技大学 |
推荐引用方式 GB/T 7714 |
Haoxiang Zhou,Haiqiao Hong,Dingbang Liu,et al. RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate[C],2023:1-5.
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条目包含的文件 | 条目无相关文件。 |
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