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题名

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

作者
通讯作者Lin,Longyang; Zhang,Panpan; Yida,Li
共同第一作者Wang,Wenhui; Li,Ke
发表日期
2023-09-28
DOI
发表期刊
EISSN
2041-1723
卷号14期号:1
摘要

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µ /µ) of 85/140 cm/V·s is presented here. The ZnO TFT was integrated with HfO RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

相关链接[Scopus记录]
收录类别
语种
英语
重要成果
NI论文
学校署名
第一 ; 共同第一 ; 通讯
WOS记录号
WOS:001080410400006
Scopus记录号
2-s2.0-85173084240
来源库
Scopus
引用统计
被引频次[WOS]:10
成果类型期刊论文
条目标识符http://sustech.caswiz.com/handle/2SGJ60CL/602303
专题工学院_深港微电子学院
工学院_电子与电气工程系
作者单位
1.School of Microelectronics,Southern University of Science and Technology,Shenzhen,518055,China
2.Department of Electrical and Electronic Engineering,The University of Hong Kong,999077,Hong Kong
3.Shanghai Jiao Tong University,Shanghai,200240,China
4.State Key Laboratory of Information Photonics and Optical Communications,Beijing University of Posts and Telecommunications,Beijing,100876,China
第一作者单位深港微电子学院
通讯作者单位深港微电子学院
第一作者的第一单位深港微电子学院
推荐引用方式
GB/T 7714
Wang,Wenhui,Li,Ke,Lan,Jun,et al. CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor[J]. Nature Communications,2023,14(1).
APA
Wang,Wenhui.,Li,Ke.,Lan,Jun.,Shen,Mei.,Wang,Zhongrui.,...&Yida,Li.(2023).CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor.Nature Communications,14(1).
MLA
Wang,Wenhui,et al."CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor".Nature Communications 14.1(2023).
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