超导量子芯片中均一的约瑟夫森结开发

经典计算机算力的增长已经进入了瓶颈期，后摩尔时代量子计算将是有可能实现突破特定领域算力的方向。量子计算的优越性首先在算法层面得到了体现，但是量子算法的运行需要在稳定和高集成度的量子计算芯片硬件基础下才能够充分发挥。其中，超导量子计算由于可以利用传统的半导体加工技术制备，具有良好的扩展性、设计自由度和操控性，是目前最有希望实现通用量子计算的技术路线之一。

约瑟夫森结是超导量子比特的核心组件。约瑟夫森结的引入导致超导量子比特不同能级间的能级差不一致，这种非线性使得我们可以通过量子比特的频率明显分辨和操控该系统。在超导量子计算中，可以通过减小制备误差来准确控制量子比特的频率从而实现精确的量子操作和量子态控制，而量子比特的频率会随着约瑟夫森结的结电阻的微小变化而发生显著的变化，因此我们需要在工艺制备上控制约瑟夫森结的结面积和势垒厚度的误差范围，从而减小量子比特的频率与设计值的偏差，以实现量子比特的最佳性能。

然而，在制备超导量子计算芯片的过程中，约瑟夫森结经常出现实际电阻值偏离设计值的现象。为了解决这个问题，本文通过超声波处理、更低的蒸镀速率（0.3 𝑛𝑚/𝑠）和动态氧化等方法进行工艺优化。基于此优化制备的结阵列样品进行表征，结果显示，样品的良率最高达到99.6%，4 × 4 𝑚𝑚 区域内结电阻和临界电流的最小变异系数分别为1.94% 和1.91%，绝大部分4 × 4 𝑚𝑚 区域内的变异系数基本在2% − 3%，整个4 英寸晶圆上的结电阻和临界电流最小变异系数分别是5.43% 和5.42%，一定程度上证明在4 英寸衬底上制备高质量的超导量子芯片样品是可行的。优化后制备均一的约瑟夫森结工艺应用到36 个可调耦合的超导量子比特样品中，在稀释制冷机中测量得到最小标准差为0.06 𝐺𝐻𝑧，最小变异系数为1.67% 的量子比特顶点频率，量子比特的能量弛豫时间𝑇₁ 和退相干时间𝑇₂ 也展示出了良好的均一性。

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