Behavioral Modeling of A High-Resolution Sigma-Delta Analog-to-Digital Converter

Peng Huang1; Xichen Duan1; Jie Liang1; Liuyang Zhang2

10.1109/EIECS59936.2023.10435402

2023

979-8-3503-1668-1

2023 3rd International Conference on Electronic Information Engineering and Computer Science (EIECS)

903-906

22-24 Sept. 2023

Changchun, China

A 24-bit high-resolution sigma-delta analog-to-digital converter (ADC) with 4th-order, 3-bit quantization, and cascaded integrators feed-forward (CIFF) topology is presented in this paper. The ADC is simulated in Simulink with non-ideal factors such as clock jitter, thermal noise, op-amp noise, and non-ideal integrators are analyzed and modeled. The simulation shows that the signal-to-noise ratio (SNR) of the non-ideal model is 136.6 dB and the effective number of bits (ENOB) is 22.73 bits. The sigma-delta ADC satisfies the requirements of high-precision conversion in a variety of industrial measurement scenarios (such as detection and navigation, biosensing, etc.) and medical treatment.

modulator high-resolution ADC noise shaping oversampling

其他

IEEE

1.School of Microelectronics, Shanghai University, Shanghai, China
2.School of Microelectronics, Southern University of Science and Technology, Shenzhen, China

Peng Huang,Xichen Duan,Jie Liang,et al. Behavioral Modeling of A High-Resolution Sigma-Delta Analog-to-Digital Converter[C],2023:903-906.