高性能 GaN p-FET 器件关键工艺研究

氮化镓（GaN）作为第三代半导体的代表材料，具有宽禁带，高电子 迁移率和高临界场强的优势，目前已在消耗电子、5G 通讯、军用雷达等领 域得到广泛应用。相对现在商业应用的分立器件，氮化镓单片集成技术可 以有效避免 GaN 分立器件存在的寄生效应过大的问题，充分发挥出 GaN 器 件的性能优势，已成为研究热点。基于 GaN n 沟道和 p 沟道器件的互补金 属氧化物半导体（CMOS）技术具有低静态功率损耗、低电路复杂程度、 高节能效果的优势，成为更为优选的方案和推动下一代技术应用的新爆发 点。然而，GaN p-FET 器件作为 CMOS 技术中的基本单元，依然存在 p-GaN 材料本征特性引起的难以形成低阻欧姆接触和刻蚀损伤过大等问题，造成 其各项器件性能水平与 n 沟道 GaN 器件相比仍然存在较大差距，高性能 GaN p-FET 器件的缺失严重限制了 GaN CMOS 技术的发展。本课题从 GaN p-FET 器件的关键工艺出发，针对器件的低阻欧姆接触和低损伤刻蚀技术 开展系统研究。

本课题为实现低阻欧姆接触，创新引入旋涂玻璃工艺对 GaN 表面进行 处理，处理后欧姆接触阻值由未处理的 1.3×10-3 Ω·cm2 下降到 1.2×10-4 Ω·cm2。进一步利用能量色散 X 射线光谱仪表征金属和外延界面的表面成分 变化，利用二次离子质谱测试不同 SOG 工艺退火温度下的关键元素浓度分 布，发现 SOG 处理工艺能显著提高源、漏区域镁掺杂浓度，实现工艺简单、 无损伤的选区表面镁掺杂，相应减小欧姆接触阻值。此外，本课题分别研 究了氯气连续刻蚀、含氧连续刻蚀和新型原子层刻蚀三种不同刻蚀方法， 从刻蚀速率、刻蚀深度控制和表面形貌等维度进行综合对比分析，表征刻 蚀后的表面成分，研究不同刻蚀方法的作用机理，探索不同刻蚀工艺的最 优化应用场景。在此基础上，通过结合较高速率的氯气连续刻蚀和低损伤 原子层刻蚀两种刻蚀技术，实现综合性能最优的复合刻蚀工艺。本课题主 要研究了 GaN p-FET 上的欧姆接触和刻蚀两个关键工艺及其相应机理，为 后续 GaN CMOS 技术开发奠定基础。

Gallium Nitride (GaN), as the typical third-generation semiconductor materials, has advantages like wide bandgap, high electron mobility, and high critical field strength. It has been widely used in the field of power electronics, 5G communication, and military radar. Compared to GaN discrete devices currently used in commercial applications, GaN monolithic integration technology can effectively avoid the issues of excessive parasitic effects. This enables GaN devices to fully leverage their performance advantages. GaN complementary metal-oxide-semiconductor (CMOS) technology based on n-channel and p-channel devices offers low static power loss, low circuit complexity and high energy efficiency. These advantages make it a preferred solution and a driving force for the next generation of technological breakthroughs. However, as the basic unit in CMOS technology, GaN p-FET devices still suffer from difficulties in forming low-resistance Ohmic contact and excessive etch damage. This results in significant performance gaps between GaN p-FET devices and n-channel GaN devices, severely limiting the development of GaN CMOS technology. This study focuses on the development and related mechanisms of low-resistance Ohmic contact and low damage etching for GaN p-FET devices.

In this study, an innovative spin-on glass (SOG) process is introduced to treat the surface of GaN to achieve low-resistance Ohmic contact. After SOG treatment, the resistance of the Ohmic contact was increased from 1.28×10^-3 Ω·cm² for untreated sample to 1.2×10^-4 Ω·cm². Furthermore, surface composition changes of the metal and epitaxial interface are characterized using energy-dispersive X-ray spectroscopy. The distribution of key element concentrations under different SOG annealing temperatures is characterized using secondary ion mass spectrometry. Experimental results show that SOG treatment significantly increases the magnesium doping concentration in the source and drain regions. This achieves selective surface doping with a simple and non-destructive approach and correspondingly decreases the resistance. Additionally, three different etching methods, including continuous chlorine etching, oxygen-containing continuous etching and novel atomic layer etching, are investigated. A comprehensive comparative analysis is conducted to analyzed etching rate, control of etching depth and surface morphology. Surface composition after etching process is characterized and the primary mechanisms of different etching methods are studied. An etching process combined higher-rate continuous chlorine etching with low-damage atomic layer etching is promoted. This study primarily focuses on Ohmic contact and etching process for GaN p-FETs, laying the foundation for the development of high-performance GaN CMOS technology.

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