面向CMOS应用的GaN p-FETs关键技术研究

氮化镓互补金属氧化物半导体（Gallium Nitride Complementary Metal Oxide Semiconductor，GaN CMOS）技术具有简单驱动、低损耗、与存储器件兼容、可创建更多芯片功能等诸多优势，成为高压及大功率电力电子应用领域的重点发展对象。而作为CMOS基本单元之一的增强型GaN p沟道场效应晶体管（p-channel Field-Effect Transistor，p-FETs）却面临着源、漏极欧姆接触制备困难和栅极刻蚀损伤严重的挑战。这导致GaN p-FETs具有较差的导通特性并严重制约了GaN CMOS技术的发展。截止到目前，绝大多数报道显示GaN p-FETs源、漏极接触为肖特基接触，且最低接触电阻率与CMOS另一基本单元n-FETs相差2~3个数量级，距离p-FETs分立器件应用或是CMOS应用都有很大差距。此外，现有研究缺乏对凹栅刻蚀后的p-GaN表面损伤的系统分析以及刻蚀引入的界面电荷对器件栅极可靠性影响的研究，无法为提高GaN p-FETs器件性能提供理论指导。因此，开展面向CMOS应用的GaN p-FETs源、漏极欧姆接触和栅极刻蚀等关键技术的研究，对于开发高性能GaN p-FETs及推进GaN CMOS技术发展具有极为重要的研究意义和价值。

本论文围绕制备高性能GaN p-FETs面临的若干挑战，从欧姆接触基线工艺、p型GaN（p-GaN）表面氧化物去除技术、欧姆接触形成机制、栅极刻蚀损伤、刻蚀引入界面态、栅极可靠性等方面着手，针对目前GaN p-FETs在源、漏极欧姆接触和凹槽栅极刻蚀等关键技术存在的诸多问题展开研究和探讨。论文的主要研究内容如下：

1．针对GaN p-FETs欧姆接触制备困难及传统欧姆接触制备工艺基线不稳定以及欧姆接触相关机理一片空白等问题，开发出一种稳健可靠、工艺简洁、可商业化应用的新型欧姆接触制备工艺基线并揭示了欧姆接触的形成机制。研究得出，传统工艺基线中的弱氧等离子体去除光刻胶步骤会氧化p-GaN并形成GaO_x屏障，从而抑制欧姆接触的形成。退火氛围中的O₂诱导界面生成的p型Ni₂O₃和高浓度Ga空位是金属与p-GaN形成稳定欧姆接触的原因。

2．针对传统酸溶液去除p-GaN表面GaO_x技术存在的p-GaN表面再氧化及化学溶液残留影响器件可靠性等问题，创新性地研究出基于镁接触层的原位GaO_x去除技术。随后针对GaN p-FETs上低阻欧姆接触制备困难的现状，基于Mg/Pt/Au新型金属结构，研发出具有12 Ω·mm的超低接触电阻率欧姆接触，将已报道的接触电阻率最优水平提升了近7倍。最后得出，高功函数金属与p-GaN的直接接触，以及扩散至界面处的Au诱导产生的Ga空位是形成超低接触电阻率欧姆接触的原因。

3．针对GaN p-FETs欧姆接触现有报道在金属/p-GaN界面载流子传输机制研究方面的空白，首次揭示了具有超低接触电阻率的Mg/Pt/Au欧姆接触的界面载流子传输机制。研究得出，接触层中的Mg原子会在RTA过程中向内扩散并使p-GaN表面形成重掺杂层。这导致当测试温度>340 K时，Mg/Pt/Au欧姆接触的金属/p-GaN界面载流子沿着价带流动；而在200~340 K时，载流子沿着Mg相关的深能级缺陷带流动且有效势垒高度仅为0.265 eV。

4．针对目前有Au欧姆接触工艺导致的GaN CMOS技术无法导入成熟Si CMOS无Au工艺线的问题，创新研发无Au GaN p-FETs欧姆接触。研究得出，Mg/Ni/Pt欧姆接触实现了8 Ω·mm的超低接触电阻率，这一数值已超越当前已报道的最优数值。随后揭示出Ni诱导产生的Ga空位以及界面形成的p型半导体Ni₂O₃有效降低了金属与p-GaN间的接触势垒高度，从而导致超低接触电阻率无Au欧姆接触的形成。

5．针对现有研究报道缺乏对凹栅刻蚀后p-GaN表面损伤以及刻蚀引入界面态对器件栅极可靠性的系统性分析，开展了相关研究。研究发现，低功率的纯BCl₃刻蚀菜单实现了4.5 nm/min的超慢速p-GaN刻蚀，并且具有刻蚀表面粗糙度低、台阶边缘毛刺少及刻蚀倾角接近90°的优势。此外，良好的刻蚀形貌是制备增强型凹槽栅GaN p-FETs的关键，但刻蚀引入了10¹²~10¹³ cm^-2eV^-1的高密度缺陷态，严重影响了器件栅极可靠性及高温工作能力。

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