可扩展超导量子芯片的设计与制备工艺研究

基于约瑟夫森结的超导量子计算线路因其出色的可扩展性和可操作性被认为是实现通用量子计算最有前景的方案之一。而超导量子比特芯片作为超导量子计算的核心器件，其设计与制备工艺直接决定了量子计算物理实现的结果。对于超导量子芯片来说，通过仿真和模拟优化出的一个合理且可靠的设计可以大幅度缩短样品迭代的进度。同时一个高精度且连续可控的标准化芯片制备工艺，对于超导量子计算的应用与发展至关重要，它确保了实验的重复性和芯片性能的一致性。

尽管超导量子计算领域近年来已取得显著进展，但目前进行实验的超导量子芯片与实现真正通用量子计算所需的芯片性能之间还存在较大的技术差距。对于超导量子计算来说，为了构建具有足够多逻辑比特，能够进行实用化计算的量子线路可能需要数百万个物理量子比特。然而目前即使是领域内技术最先进的量子计算芯片，其拥有的比特数目也不足以编码可以实现有效量子纠错的逻辑比特。所以设计与开发具有可扩展性的超导量子比特架构和加工工艺对未来通用量子计算
的实现具有极其重要的意义。

本文通过剖析超导量子比特的工作原理以及微纳加工的基本工艺，探索了一套从设计到制备芯片的完整流程。同时为提高比特门操作的保真度，提出了一种创新的、具有高度可扩展性的超导量子比特设计方案。该方案采用了一种独特的耦合器开关机制，通过调制耦合器频率实现两个比特之间的精确耦合控制。后续基于该方案独立设计和制备的样品上成功实现了一个保真度高99.5% 的两比特CZ 门的操作，同时通过充分利用对两量子比特系统单激发子空间的完全可控性，实现了g-框架模拟的动态解耦序列，并展示了有效抑制交换退相干的能力。鉴于平面样品芯片在可扩展性上的局限性，本文提供了一种基于倒装焊技术的三维（3D）芯片设计方案及其加工流程，有效解决了传统平面芯片在布线复杂度和扩展性上的局限，并通过倒装焊结构优化了比特的设计从而有效地减少了准粒子噪声。后续成功将此方案应用于倒装66 比特芯片的物理实现上，芯片上66 个比特和110个耦合器存活率为100%，最高T1达到147 μs。本文所提供的设计方案与工艺细
节将为未来进一步扩展超导量子芯片的规模打下坚实的基础。

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