中文版 | English
题名

MOSFET阈值电压及金属互联电阻低温模型研究及其在LC振荡器低温设计上的应用

其他题名
Research on Cryogenic Model of MOSFET Threshold Voltage and Metal Interconnect Resistance and Their Application in Cryogenic LC Oscillator Design
姓名
姓名拼音
CAI Yiyuan
学号
12132434
学位类型
硕士
学位专业
080903 微电子学与固体电子学
学科门类/专业学位类别
08 工学
导师
陈凯
导师单位
深港微电子学院
论文答辩日期
2024-05
论文提交日期
2024-07-04
学位授予单位
南方科技大学
学位授予地点
深圳
摘要

量子计算被认为是最有可能在后摩尔定律时代实现颠覆性算力的重要 技术路线之一,近二十年来受到了日益广泛的关注而处于高速发展阶段。 其中基于超导和硅基这两种量子比特的路径尤为受到国际科技巨头的青睐, 而这两种技术均需要将量子比特置于 100 mK 甚至更低的超低温环境下。 在量子计算机发展的早期,由于量子比特数目较少,对超低温区量子比特 的控制与测量是通过缆线接入的方式进行。但随着量子比特的增多,当前 主流方式是将具有测控功能的CMOS芯片置入4 K温区,与处于超低温的 量子比特进行对接。未来则有将量子比特与 CMOS 测控电路进一步通过不 同技术手段集成实现单芯片的技术设想,由此超低温 CMOS 技术(cryo CMOS)便应运而生。

超低温 CMOS 因其高集成性的特点,可以极大的提高量子计算机的拓 展性和性能。虽然 CMOS 技术目前已具有优秀的集成特性和完善的产业基 础。但作为量子计算的周围电路设计使用仍然缺乏模型指导,严重阻碍了 超低温电路的研究。

本文所介绍的工作主要分为三大部分,均基于台积电(TSMC)标准 CMOS 180 nm 和 40nm 两个工艺节点的设计及流片结果:首先是对有源 (active)MOS 晶体管关键参数阈值电压的建模工作,即对标准 NMOS 和 PMOS 器件阵列进行设计和流片,随后在对多个超低温测试平台进行实验 摸索的基础上,在不同温区对所流片的MOS器件进行测试与表征,并基于 实验测试数据萃取 MOSFET 的关键参数,通过分析低温下影响阈值电压的 物理机制,针对大尺寸器件阈值电压建立了物理解析模型;其次是对 CMOS 片上无源(passive)金属互联电阻在宽温区的模型分析研究及 Verilog-A 实现,并在宽温区进行测试,将实验测试结果与模型进行拟合; 最后是结合金属互联电阻模型与超低温 MOSFET 器件特性,对宽温区下 LC 振荡器的振荡情况进行定量分析,对比振荡器表征数据,由此可以较好 地预测低温下LC振荡器的工作状态。

关键词
语种
中文
培养类别
独立培养
入学年份
2021
学位授予年份
2024-06
参考文献列表

[1] Moore G E. Cramming More Components onto Integrated Circuits[J]. PROCEEDINGS OF THE IEEE, 1998, 86(1).
[2] Feynman R P. Simulating physics with computers[J].
[3] Lambropoulos P, Petrosyan D. Fundamentals of quantum optics and quantum information[M]. Berlin ; New York: Springer, 2007.
[4] Almudever C G, Lao L, Fu X, et al. The engineering challenges in quantum computing[J]. 2017.
[5] Bardin J C, Jeffrey E, Lucero E, et al. 29.1 A 28nm Bulk-CMOS 4-to-8GHz ¡2mW Cryogenic Pulse Modulator for Scalable Quantum Computing[C]//2019 IEEE International Solid- State Circuits Conference - (ISSCC). San Francisco, CA, USA: IEEE, 2019: 456-458.
[6] Charbon E, Sebastiano F, Babaie M, et al. 15.5 Cryo-CMOS circuits and systems for scalable quantum computing[C]//2017 IEEE International Solid-State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2017: 264-265.
[7] Cheng Y, Jeng M C, Liu Z, 等. A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation[J]. IEEE Transactions on Electron Devices, 1997, 44(2): 277-287.
[8] Pahwa G, Kushwaha P, Dasgupta A, et al. Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures[J]. IEEE Transactions on Electron Devices, 2021, 68(9): 4223-4230.
[9] Incandela R M, Song L, Homulle H A R, et al. Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures[C]//2017 47th European Solid-State Device Research Conference (ESSDERC). Leuven, Belgium: IEEE, 2017: 58-61.
[10] Beckers A, Jazaeri F, Bohuslavskyi H, et al. Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing[C]//2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). Granada: IEEE, 2018: 1-4.
[11] Beckers A, Beckers D, Jazaeri F, et al. Generalized Boltzmann relations in semiconductors including band tails[J]. Journal of Applied Physics, 2021, 129(4): 045701.
[12] Beckers A, Jazaeri F, Grill A, et al. Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs[J]. IEEE Journal of the Electron Devices Society, 2020, 8: 780-788.
[13] Beckers A, Jazaeri F, Enz C. Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K[J]. IEEE Journal of the Electron Devices Society, 2018, 6: 1007-1018.
[14] Chakraborty W, Aabrar K A, Gomez J, 等. Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS[J]. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021, 7(2): 184-192.
[15] Grill A, John V, Michl J, et al. Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors[C]//2022 IEEE International Reliability Physics Symposium (IRPS). Dallas, TX, USA: IEEE, 2022: 10A.1-1-10A.1-6.
[16] T Hart P A, Babaie M, Charbon E, et al. Characterization and Modeling of Mismatch in Cryo-CMOS[J]. IEEE Journal of the Electron Devices Society, 2020, 8: 263-273.
[17] Schriek E, Sebastiano F, Charbon E. A Cryo-CMOS Digital Cell Library for Quantum Computing Applications[J]. IEEE Solid-State Circuits Letters, 2020, 3: 310-313.
[18] Saligram R, Datta S, Raychowdhury A. Scaled Back End of Line Interconnects at Cryogenic Temperatures[J]. IEEE Electron Device Letters, 2021, 42(11): 1674-1677.
[19] Patra B, Mehrpoo M, Ruffino A, et al. Characterization and Analysis of On-Chip Microwave Passive Components at Cryogenic Temperatures[J]. IEEE Journal of the Electron Devices Society, 2020, 8: 448-456.
[20] Homulle H, Sebastiano F, Charbon E. Deep-Cryogenic Voltage References in 40-nm CMOS[J]. IEEE Solid-State Circuits Letters, 2018, 1(5): 110-113.
[21] Mehrpoo M, Sebastiano F, Charbon E, 等. A Cryogenic CMOS Parametric Amplifier[J]. IEEE Solid-State Circuits Letters, 2020, 3: 5-8.
[22] Kiene G, Catania A, Overwater R, 等. 13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS[C]//2021 IEEE International Solid- State Circuits Conference (ISSCC): 卷 64. 2021: 214-216.
[23] Gong J, Charbon E, Sebastiano F, 等. A Cryo-CMOS PLL for Quantum Computing Applications[J]. IEEE Journal of Solid-State Circuits, 2022: 1-14.
[24] Guo Y, Liu Q, Li T, et al. Cryogenic CMOS RF Circuits: A Promising Approach for Large-Scale Quantum Computing[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(3): 1619-1625.
[25] Caglar A, Winckel S V, Brebels S, 等. Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout[J]. IEEE Journal of Solid-State Circuits, 2022: 1-11.
[26] Peng Y, Benserhir J, Castaneda M, et al. A 0.32 X 0.12 mm^2 Cryogenic BiCMOS 0.1–8.8 GHz Low Noise Amplifier Achieving 4 K Noise Temperature for SNWD Readout[J]. IEEE Transactions on Microwave Theory and Techniques, 2024: 1-14.
[27] Patra B, Van Dijk J P G, Subramanian S, et al. 19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers[C]//2020 IEEE International Solid- State Circuits Conference - (ISSCC). San Francisco, CA, USA: IEEE, 2020: 304-306.
[28] Guo Y, Li Y, Huang W, et al. A Polar-Modulation-Based Cryogenic Qubit State Controller in 28nm Bulk CMOS[C]//2023 IEEE International Solid- State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2023: 508-510.
[29] Yoo J, Chen Z, Arute F, et al. 34.2 A 28-nm Bulk-CMOS IC for Full Control of a Superconducting Quantum Processor Unit-Cell[C]//2023 IEEE International Solid- State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2023: 506-508.
[30] Guevel L L, Billiot G, Jehl X, et al. 19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot[C]//2020 IEEE International Solid- State Circuits Conference - (ISSCC). San Francisco, CA, USA: IEEE, 2020: 306-308.
[31] Pauka S J, Das K, Kalra R, et al. A cryogenic CMOS chip for generating control signals for multiple qubits[J]. Nature Electronics, 2021, 4(1): 64-70.
[32] Zhang Y, Lu T, Wang W, 等. Characterization and Modeling of Native MOSFETs Down to 4.2 K[J]. IEEE Transactions on Electron Devices, 2021, 68(9): 4267-4273.
[33] Li Z, Luo C, Lu T, et al. Cryogenic Characerization and Modeling of Standard CMOS down to Liquid Helium Temperature for Quantum Computing[M]. arXiv, 2019.
[34] Tang Z, Wang Z, Guo A, 等. Cryogenic CMOS RF Device Modeling for Scalable Quantum Computer Design[J]. IEEE Journal of the Electron Devices Society, 2022, 10: 532-539.
[35] Wang Z, Tang Z, Guo A, et al. Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs[J]. IEEE Electron Device Letters, 2020, 41(5): 661-664.
[36] Zhang G, Lin H, Wang C. 34.5 A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with 202dBc/Hz FoM for Classic-Quantum Interface[C]//2023 IEEE International Solid- State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2023: 512-514.
[37] bsim330_manual.pdf[Z].
[38] Cassé M, Tachi K, Thiele S, et al. Spectroscopic charge pumping in Si nanowire transistors with a high-κ/metal gate[J]. Applied Physics Letters, 2010, 96(12): 123506.
[39] Beckers A, Jazaeri F, Bohuslavskyi H, et al. Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures[J]. Solid-State Electronics, 2019, 159: 106-115.
[40] Matula R A. Electrical resistivity of copper, gold, palladium, and silver[J]. Journal of Physical and Chemical Reference Data, 1979, 8(4): 1147-1298.
[41] Lopez G, Davis J, Meindl J. A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER)[J].
[42] Lt Hart P A, Huizinga T, Babaie M, et al. Integrated Cryo-CMOS Temperature Sensors for Quantum Control ICs[C]//2022 IEEE 15th Workshop on Low Temperature Electronics (WOLTE). Matera, Italy: IEEE, 2022: 1-4.
[43] T Hart P A, Babaie M, Vladimirescu A, et al. Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures[J]. IEEE Journal of the Electron Devices Society, 2021, 9: 891-901.
[44] Saligram R, Chakraborty W, Cao N, et al. Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models[J]. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021, 7(2): 193-200.

所在学位评定分委会
电子科学与技术
国内图书分类号
TN386.1
来源库
人工提交
成果类型学位论文
条目标识符http://sustech.caswiz.com/handle/2SGJ60CL/778985
专题南方科技大学-香港科技大学深港微电子学院筹建办公室
推荐引用方式
GB/T 7714
蔡乙源. MOSFET阈值电压及金属互联电阻低温模型研究及其在LC振荡器低温设计上的应用[D]. 深圳. 南方科技大学,2024.
条目包含的文件
文件名称/大小 文献类型 版本类型 开放类型 使用许可 操作
12132434-蔡乙源-南方科技大学-(6429KB)----限制开放--请求全文
个性服务
原文链接
推荐该条目
保存到收藏夹
查看访问统计
导出为Endnote文件
导出为Excel格式
导出为Csv格式
Altmetrics Score
谷歌学术
谷歌学术中相似的文章
[蔡乙源]的文章
百度学术
百度学术中相似的文章
[蔡乙源]的文章
必应学术
必应学术中相似的文章
[蔡乙源]的文章
相关权益政策
暂无数据
收藏/分享
所有评论 (0)
[发表评论/异议/意见]
暂无评论

除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。