基于氧化铟镓锌动态随机存储器的精度重构型存内计算

  随着人工智能技术的快速进步，软件算法对硬件芯片系统的要求越来 越高。但是，一方面，芯片产业进入“后摩尔时代”，依靠器件尺寸微缩 的设计方案已不再适用；另一方面，在传统的冯诺依曼架构中，存储单元 和计算单元的分离，造成“功耗墙”与“内存墙”等问题。基于新型存储器的存内计算方案为此提供了一套可行的解决方案。例如近年来备受关注的氧化铟镓锌（IGZO）动态随机存储器（DRAM），由于其晶体管关断电流小，而具备非易失性、功耗小、多电导状态特性，且晶体管读取速度快，与 CMOS 工艺兼容。因此，基于 IGZO-DRAM 的存内计算架构在面向边缘 智能部署的神经网络加速器领域展现了巨大的潜力。然而，该类型的存算体系主要面临计算准确性和高效性互斥的问题。 传统基于模拟域存内计算（例如基于差分架构的存算）的方案一方面采用了双倍的存储器件和运放模块，另一方面也存在严重的计算误差问题。常 规采用数字型重构计算的方案可以实现高精度计算，但耗费了数倍的存储 和数模转换单元，降低了效率。近年来，一种被称之为数模混合计算重构的方案被提出，可有效兼顾计算准确性和高效性。本论文对这一方案开展 了更深入的研究，我们利用高比特 IGZO-DRAM 的器件特性，提出了基于 多电导状态数分割的重构方案。并且设计了一套通用的电导状态的映射关系，搭建了数值仿真平台分别对有符号单乘法器和乘法累加器进行仿真。我们还对精度重构方案中的最优分割进行了分析。并提出了一种适用于从任意状态数出发的满电导状态重构模型，允许精度重构在非整比特状态数 下进行。之后我们对每种最大状态数下最优分割方案进行了研究，设计实现了一套可以推广至任意位宽的通用型精度重构方案算法。统计了单乘法器和乘法累加器在不同重构方案下的误差，探究了不同器件最大状态数下，最优方案可能存在的分割规律。最后我们使用提出的精度重构型存内计算方案在 LeNet-5 神经网络和 VGG 类神经网络上进行仿真，在两种情况下都得到了十分可观的识别准确率，展现了基于 IGZO-DRAM的精度重构方案在神经网络中实现高精度高能效计算的优势。

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