题名 | A Fully-Integrated Flexible Dual-Ring Switched-Capacitor DC-DC Converter With Fractional VCRs and Parasitic Reduction |
作者 | |
通讯作者 | Lu, Yan; Jiang, Junmin |
发表日期 | 2024-06-01
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DOI | |
发表期刊 | |
ISSN | 1549-8328
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EISSN | 1558-0806
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摘要 | This paper presents a fully-integrated flexible dual-ring switched-capacitor (SC) converter to address the limited output voltage resolution in conventional SC converters. Based on the concept of reconfiguring multiple SC cells in series, the proposed dual-ring SC (DRSC) converter offers various combinations of cascading stages through the outer main ring configuration. Furthermore, the inner sub-ring operation allows for a more flexible selection of output nodes, enabling different power path interconnections and increasing the number of available voltage conversion ratios (VCRs). With 9 fractional VCRs, the converter offers a wide output range and fine output resolution. Compared to traditional SC topologies, the proposed topology exhibits the lowest slow switching limit resistance (R-SSL) and the most favorable G-V-2 metric, indicating high power efficiency. In addition, to reduce the parasitic capacitance, triple-well junction capacitors with increased reverse bias voltage were proposed. Parasitic capacitance with as low to 0.4% of the main capacitance was achieved. 3.9% efficiency improvement was measured. The chip was fabricated in a 180nm CMOS process and measured with 83% peak efficiency and 200mA maximum load current. |
关键词 | |
相关链接 | [来源记录] |
收录类别 | |
语种 | 英语
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学校署名 | 通讯
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资助项目 | National Natural Science Foundation of China["62122001","62104093"]
; Macao Science and Technology Development Fund (FDCT)[0103/2022/AFJ]
; Guangdong Basic and Applied Basic Research Foundation[2022A1515010557]
; Shenzhen Fundamental Research Program[JCYJ20220818100609021]
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WOS研究方向 | Engineering
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WOS类目 | Engineering, Electrical & Electronic
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WOS记录号 | WOS:001258823500001
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出版者 | |
ESI学科分类 | ENGINEERING
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来源库 | Web of Science
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引用统计 | |
成果类型 | 期刊论文 |
条目标识符 | http://sustech.caswiz.com/handle/2SGJ60CL/783783 |
专题 | 工学院_电子与电气工程系 |
作者单位 | 1.Univ Macau, Inst Microelect, State Key Lab Analog Mixed Signal VLSI, Taipa, Macau, Peoples R China 2.Univ Macau, FST DECE, Macau, Peoples R China 3.Southern Univ Sci & Technol, Dept Elect & Elect Engn, Shenzhen 518055, Peoples R China |
第一作者单位 | 电子与电气工程系 |
通讯作者单位 | 电子与电气工程系 |
推荐引用方式 GB/T 7714 |
Jiang, Yifan,Lu, Yan,Jiang, Junmin. A Fully-Integrated Flexible Dual-Ring Switched-Capacitor DC-DC Converter With Fractional VCRs and Parasitic Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2024.
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APA |
Jiang, Yifan,Lu, Yan,&Jiang, Junmin.(2024).A Fully-Integrated Flexible Dual-Ring Switched-Capacitor DC-DC Converter With Fractional VCRs and Parasitic Reduction.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS.
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MLA |
Jiang, Yifan,et al."A Fully-Integrated Flexible Dual-Ring Switched-Capacitor DC-DC Converter With Fractional VCRs and Parasitic Reduction".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2024).
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