13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS

Weitao Wu; Hongzhi Wu; Liping Zhong; Xuxu Cheng; Xiongshi Luo; Dongfan Xu; Catherine Wang; Zhenghao Li; Quan Pan

10.1109/ISSCC49657.2024.10454320

2024-02-22

0193-6530

979-8-3503-0621-7

2024 IEEE International Solid-State Circuits Conference (ISSCC)

67

18-22 Feb. 2024

San Francisco, CA, USA

With the development of massive computing and AI technologies, the memory interface is critical to achieve higher computational throughput. Increasing the parallel-channel density is an effective solution to improve the throughput [1]. However, due to a reduced channel pitch, the crosstalk between adjacent lanes becomes severe and degrades signal integrity. Advanced DRAM applications, such as GDDR6x [2], have adopted PAM-4 signaling to increase transmission speed; unfortunately, PAM-4 is more sensitive to crosstalk. Various TX crosstalk cancellation (XTC) techniques have been reported [3] –[5], but these techniques mainly focus on NRZ. The de-emphasis FIR-based XTC (FIR-XTC) in [3] increases static power consumption and reduces the TX-output SNR. Phase predistortion is utilized in [4] to eliminate crosstalk; however, this method has limited elimination capacity and high-power consumption. Fibonacci coding used in [5] decreases the pin efficiency by 25% and consumes substantial power for PAM-4, due to the increased coding complexity. Therefore, an efficient PAM-4 crosstalk cancellation technique that does not sacrifice pin efficiency and the TX-output SNR is highly desired.

第一

EI

Southern University of Science and Technology, Shenzhen, China

Weitao Wu,Hongzhi Wu,Liping Zhong,et al. 13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS[C],2024.