Warpage Control Method in Fan-Out Wafer Level Packaging with Rectangular Chips

Zhenghan Yan1; Cheng Zhong2; Pengcheng Jiang2; Chi Ma2; Shuang Liu2; Dan Zeng2; Hong Wang2; Zhengxun Hu2; Rong Sun2

10.1109/ICEPT59018.2023.10491984

2023-08-11

2836-9734

979-8-3503-3882-9

2023 24th International Conference on Electronic Packaging Technology (ICEPT)

8-11 Aug. 2023

Shihezi City, China

Fan-out wafer level packaging (FOWLP) is an enhancement of general wafer-level packaging developed to provide a solution for devices requiring a higher integration level and a greater number of external contacts. Compared to traditional packaging, FOWLP has strong advantages in packaging thickness, manufacturing costs, power consumption, and signal integrity. Considering the technical advantages and market forecast of FOWLP, it has the potential to become a preferred packaging technology for the next generation of portable mobile device chips. However, due to the influence of geometry structure or material distribution, there may be some differences in bending stiffness in different directions of the wafer, resulting in asymmetric warpage, which is also known as warpage bifurcating behavior. In addition, in fan-out packaging, most of the silicon chips are rectangular, i.e., the length and width of which are different, which will inevitably lead to serious asymmetric warpage after the process of the reconstituted wafer. Therefore, to reduce or even avoid the influence of asymmetric warpage in FOWLP, it is necessary to analyze the evolution of asymmetric warpage, explore the reasons for asymmetric warpage, and propose reasonable warpage control methods.In this paper, the asymmetric warpage process of the reconstituted wafer caused by package structure is analyzed by finite element analysis (FEA) and experiential verification, and the reasons of asymmetric warpage are explained in detail. Keeping the fan-out ratio, two warpage control methods are proposed by optimizing the chip layout, namely "dummy replacement method" and "interval arrangement method". Compared with the traditional layout method, the "dummy replacement method" can effectively improve the warpage morphology and reduce the warpage value. At room temperature, the warpage value decreased by 34.9%, but obvious asymmetric warpage still happens after debonding. The "interval arrangement method" shows a better result on warpage morphology, and maintains a relatively uniform warpage distribution after debonding, the warpage value decreases up to 47.3%.

第一

1.Shenzhen Institute of Advanced Electronic Materials, Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences Southern University of Science and Technology, Shenzhen, China
2.Shenzhen Institute of Advanced Electronic Materials, Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China

Zhenghan Yan,Cheng Zhong,Pengcheng Jiang,et al. Warpage Control Method in Fan-Out Wafer Level Packaging with Rectangular Chips[C],2023.