Simulation of performance and reliability of nanocopper paste in power device packaging

Tongtong Wang1,2; Liang Xu1; Pengli Zhu1; Tao Zhao1; Rong Sun1

10.1109/ICEPT59018.2023.10492164

2023-08-11

2836-9734

979-8-3503-3882-9

2023 24th International Conference on Electronic Packaging Technology (ICEPT)

8-11 Aug. 2023

Shihezi City, China

With integrated circuits and semiconductor technology development, chip packaging tends to be miniaturized and highly integrated. The advent of third-generation wide-bandgap (WBG) semiconductors such as SiC and GaN, which allow chips to operate at high temperatures (above 300°C), poses a major challenge for chip packaging. Chip attachments are key to achieving reliable operation of power semiconductor devices, as they play an important role in the physical and electrical connection of the chip to the substrate. For this, metal particles are considered an ideal choice because of their low sintering temperature, high performance and reliability under extreme conditions. Sintered silver pastes have received increasing attention as a new method of chip connection. However, the practical application of sintered silver is very limited due to its high cost and low resistance to electromigration. Copper is known to be much cheaper than silver and has similar electrical and thermal conductivity to silver. More importantly, copper has excellent resistance to electromigration. These unique properties make it a very promising material for chip connections. There have been some reports on the reliability assessment of sintered silver materials, but very little has been reported on sintered copper materials.In this paper, a detailed analysis of the stress-strain variation pattern of the sintered copper layer during temperature cycling (TC) and power cycling (PC) of a typical planar MOSFET device is presented using finite element analysis. In PC, the relationship between heating power and temperature is investigated using a coupled thermal-force approach, and the effect of temperature variations inside the device on the stress in the sintered copper layer is analyzed. In addition, we have constructed the chip under ideal conditions and investigated the key factors affecting the stresses in the connecting layer of the chip during temperature cycling, thus providing assistance in reducing stresses and improving reliability. Our work aims to offer assistance in the qualitative and quantitative evaluation of the operational lifespan of power devices.

其他

1.Shenzhen Institute of Advanced Electronic Materials, Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China
2.Southern University of Science and Technology, Shenzhen, China

Tongtong Wang,Liang Xu,Pengli Zhu,et al. Simulation of performance and reliability of nanocopper paste in power device packaging[C],2023.