A Parallel Acceleration Technique based on Bordered Block Diagonal Matrix Reordering for Exponential Integrator Method

Hang Zhou1,2; Dongen Yang1,2; Yangfei Lin1,2; Yong Dai1,2; Quan Chen1,2

10.1109/ISEDA62518.2024.10617631

2024-05-13

979-8-3503-5204-7

2024 2nd International Symposium of Electronics Design Automation (ISEDA)

10-13 May 2024

Xi'an, China

The exponential integrator (EI) method has proven to be an effective technique to accelerate transient circuit simulation. One core step of EI is the generation of rational Krylov subspace basis by the Arnoldi process, which involves one (exact) LU factorization and many back/forward trian-gular solves. Traditional parallelization techniques for circuit simulation perform well in accelerating the LU factorization part (the symbolic and numerical factorization) but fall short in parallelizing the triangular solution part. In this paper, we propose a parallel Bordered Block Diagonal (BBD) matrix reordering algorithm and a parallelization based on OpenMP and MPI to accelerate triangular solutions involved in the rational Krylov space construction in EI. Parallelization is achieved by solving corresponding part of solution vector of each diagonal matrix block independently. Numerical experiments shows that our method can achieve 3.3x and 1.9x speedup under shared and distributed memory environment respectively.

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EI

1.School of Microelectronics, Southern University of Science and Technology, ShenZhen, China
2.SMiT Group Fuxin Technology Limited, Shenjiu Science and Technology Venture Futian District, ShenZhen

Hang Zhou,Dongen Yang,Yangfei Lin,et al. A Parallel Acceleration Technique based on Bordered Block Diagonal Matrix Reordering for Exponential Integrator Method[C],2024.