Toward Efficient Co- Design of CNN Quantization and HW Architecture on FPGA Hybrid-Accelerator

Yiran Zhang; Guiying Li; Bo Yuan

10.1109/ISEDA62518.2024.10617620

2024-05-13

979-8-3503-5204-7

2024 2nd International Symposium of Electronics Design Automation (ISEDA)

10-13 May 2024

Xi'an, China

Field programmable gate array (FPGA) has emerged as a promising platform for accelerating convolutional neural networks (CNNs). In this paper, we propose a low-latency CNN hybrid-accelerator system and an efficient design space exploration (DSE) method. Specifically, our targeted FPGA platform consists of different types of accelerators for two advan-tages: high concurrency and full hardware utilization (i.e., look-up tables (LUTs) and digital signal processors (DSPs)). Besides, we adopt a bandwidth-aware analytical model for system latency to consider pipeline stalls and computation cycles simultaneously. Furthermore, for the huge design space encompassing layer-wise CNN quantization and FPGA hybrid-accelerator architecture, we propose a DSE method (named DiMEGA) aimed at enhancing search efficiency, which is a differentiable method embedded by a genetic algorithm. The performance of our CNN hybrid-accelerator system is demonstrated on a PYNQ-Z2 FPGA plat-form. The experimental results show that the system latency can be reduced by 42% ~ 48% without sacrificing accuracy, and the DSE time of DiMEGA is reduced by 23% on ResNet20-CIFAR10, and 63% on ResNet56-CIFAR10, compared with SOTA.

第一

EI

Guangdong Provincial Key Laboratory of Brain-Inspired Intelligent Computation, Southern University of Science and Technology, Shenzhen, China

Yiran Zhang,Guiying Li,Bo Yuan. Toward Efficient Co- Design of CNN Quantization and HW Architecture on FPGA Hybrid-Accelerator[C],2024.