Investigation on Gate Etching and Stability of GaN p-FETs

Chuying Tang1,2; Fangzhou Du1; Chun Fu1; Chenkai Deng1,2; Yi Zhang1; Yang Jiang1; Wenchuan Tao1; Wenyue Yu1; Qing Wang1; Hongyu Yu1

10.1109/IPFA61654.2024.10691287

2024-07-18

1946-1542

979-8-3503-6061-5

2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

15-18 July 2024

Singapore, Singapore

In this work, an etching recipe whose reactive gas is BCl3 and RF power is 15W, achieved ultra-low etching rates (600s, 45nm) and excellent surface morphology. An enhanced GaN p-FETs was successfully developed, and the impact of defects introduced by p-GaN etching on the gate reliability is reverse- engineered. The results indicate that the gate/dielectric interface exists interface states with a density of 1012∼1013 cm-2eV-1, resulting in poor gate reliability and the high-temperature operational characteristics.

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1.School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
2.Harbin Institute of Technology, Harbin, China

Chuying Tang,Fangzhou Du,Chun Fu,et al. Investigation on Gate Etching and Stability of GaN p-FETs[C],2024.